Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6590262 | High voltage ESD protection device with very low snapback voltage | Kuo-Chio Liu, Jian-Hsing Lee, Ruey-Hsin Liu | 2003-07-08 |
| 6396126 | High voltage transistor using P+ buried layer | Jun-Lin Tsai, Ruey-Hsin Liu, Jei-Feng Hwang | 2002-05-28 |
| 6323074 | High voltage ESD protection device with very low snapback voltage by adding as a p+ diffusion and n-well to the NMOS drain | Kuo-Chio Liu, Jian-Hsing Lee, Ruey-Hsin Liu | 2001-11-27 |
| 6291304 | Method of fabricating a high voltage transistor using P+ buried layer | Jun-Lin Tsaz, Ruey-Hsin Liu, Jei-Feng Hwang | 2001-09-18 |
| 6265752 | Method of forming a HVNMOS with an N+ buried layer combined with N well and a structure of the same | Kou-Chio Liu, Chen-Bau Wu, Ruey-Hsin Liou | 2001-07-24 |
| 6242313 | Use of polysilicon field plates to improve high voltage bipolar device breakdown voltage | Jei-Feng Hwang, Jun-Lin Tsai, Ruey-Hsin Liou | 2001-06-05 |