Issued Patents All Time
Showing 26–50 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6469362 | High-gain pnp bipolar junction transistor in a CMOS device and method for forming the same | Wen-Ying Wen | 2002-10-22 |
| 6465294 | Self-aligned process for a stacked gate RF MOSFET device | Chaochieh Tsai, Chung-Long Chang, Ju-Yu Chang | 2002-10-15 |
| 6459613 | Current-mode identifying circuit for multilevel flash memories | Hongchin Lin, Chein-Zhi Chen | 2002-10-01 |
| 6444517 | High Q inductor with Cu damascene via/trench etching simultaneous module | Heng-Ming Hsu, Chaochieh Tsai, Ssu-Pin Ma, Chao-Cheng Chen, Liang-Kun Huang | 2002-09-03 |
| 6436787 | Method of forming crown-type MIM capacitor integrated with the CU damascene process | Wong-Cheng Shih, Tzyh-Cheang Lee, Wenchi Ting, Chih-Hsien Lin | 2002-08-20 |
| 6426250 | High density stacked MIM capacitor structure | Tzyh-Cheang Lee, Chih-Hsien Lin, Chi-Feng Huang | 2002-07-30 |
| 6424183 | Current comparator | Hong-Chin Lin, Jie-Hau Huang | 2002-07-23 |
| 6414361 | Buried shallow trench isolation and method for forming the same | Shi-Tron Lin | 2002-07-02 |
| 6404030 | Chain gate MOS structure | Ssu-Pin Ma | 2002-06-11 |
| 6359501 | Charge-pumping circuits for a low-supply voltage | Hongchin Lin, Kai-Hsun Chang | 2002-03-19 |
| 6355962 | CMOS FET with P-well with P- type halo under drain and counterdoped N- halo under source region | Mong-Song Liang | 2002-03-12 |
| 6348714 | Soi structure with a body contact | Hongchin Lin | 2002-02-19 |
| 6258641 | OTP (open trigger path) latchup scheme using triple and buried well for sub-quarter micron transistors | Mong-Song Liang | 2001-07-10 |
| 6246094 | Buried shallow trench isolation and method for forming the same | Shi-Tron Lin | 2001-06-12 |
| 6232165 | Buried guard rings and method for forming the same | — | 2001-05-15 |
| 6181542 | Method of making a stack-polysilicon capacitor-coupled dual power supply input/output protection circuit | Mong-Song Liang | 2001-01-30 |
| 6169314 | Layout pattern for improved MOS device matching | Pin-Nan Tseng, Jyh-Kang Ting | 2001-01-02 |
| 6124618 | Dynamic threshold MOSFET using accumulated base BJT level shifter for low voltage sub-quarter micron transistor | Mong-Song Liang | 2000-09-26 |
| 6088273 | Method and circuit for measuring the read operation delay on DRAM bit lines | Hongchin Lin, Chien Chen, Chia-Hsiang Sha | 2000-07-11 |
| 6083797 | Buried shallow trench isolation and method for forming the same | Shi-Tron Lin | 2000-07-04 |
| 6054344 | OTP (open trigger path) latchup scheme using buried-diode for sub-quarter micron transistors | Mong-Song Liang | 2000-04-25 |
| 6051458 | Drain and source engineering for ESD-protection transistors | Mong-Song Liang | 2000-04-18 |
| 6037622 | Charge pump circuits for low supply voltages | Hongchin Lin, Kai-Hsun Chang | 2000-03-14 |
| 5994177 | Dynamic threshold MOSFET using accumulated base BJT level shifter for low voltage sub-quarter micron transistor | Mong-Song Liang | 1999-11-30 |
| 5959488 | Dual-node capacitor coupled MOSFET for improving ESD performance | Shi-Tron Lin | 1999-09-28 |