Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417992 | Chip structure with conductive pillar and method for forming the same | Shan-Yu Huang, Ming-Da Cheng, Hsiao-Wen Chung, Ching-Wen Hsiao, LI-CHUN HUNG +1 more | 2025-09-16 |
| 12159809 | System and method for measuring device inside through-silicon via surroundings | Shuo-Wen Chang, Yu-Hsien Li, Min-Tar Liu | 2024-12-03 |
| 12007431 | Test circuit and method for operating the same | Chia-Wei Huang, WEI-JHIH WANG, Cheng-Cheng Kuo | 2024-06-11 |
| 11955392 | System and method for measuring device inside through-silicon via surroundings | Shuo-Wen Chang, Yu-Hsien Li, Min-Tar Liu | 2024-04-09 |
| 11927628 | Benchmark circuit on a semiconductor wafer and method for operating the same | CHU-FENG LIAO, HUNG-PING CHENG, Shuo-Wen Chang | 2024-03-12 |
| 11754614 | Semiconductor device and analyzing method thereof | WEI-JHIH WANG, Chia-Wei Huang, Chia-Chia Kan | 2023-09-12 |
| 11688708 | Chip structure and method for forming the same | Shan-Yu Huang, Ming-Da Cheng, Hsiao-Wen Chung, Ching-Wen Hsiao, LI-CHUN HUNG +1 more | 2023-06-27 |
| 10879135 | Overlay error and process window metrology | Shang-Wei Fang, Jing-Sen Wang, Wei-Ray Lin, Ting-Hua Hsieh, Pei-Hsuan Lee +1 more | 2020-12-29 |
| 10605855 | Method, test line and system for detecting semiconductor wafer defects | Jing-Sen Wang, Hung-Chi Chiu, Chia-Wei Huang | 2020-03-31 |
| 10510623 | Overlay error and process window metrology | Shang-Wei Fang, Jing-Sen Wang, Wei-Ray Lin, Ting-Hua Hsieh, Pei-Hsuan Lee +1 more | 2019-12-17 |
| 9995770 | Multidirectional semiconductor arrangement testing | Tseng Chin Lo, Huan Chi Tseng, Kuo-Chuan Chang, Chien-Chang Lee | 2018-06-12 |
| 8779796 | Method and apparatus for device parameter measurement | Tseng Chin Luo, Chu Fu Chen, Min-Tar Liu | 2014-07-15 |