Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12271116 | Method of measuring mask overlay using test patterns | Bo-Sen Chang, Yueh-Yi Chen, Chih-Ting Sun, Ying-Jung Chen, Kung-Cheng Lin +1 more | 2025-04-08 |
| 12183729 | Integrated circuit filler and method thereof | Molly Chang, Ya-Wen Tseng, Chih-Ting Sun, Zi-Kuan Li, Bo-Sen Chang +1 more | 2024-12-31 |
| 11776948 | Integrated circuit filler and method thereof | Molly Chang, Ya-Wen Tseng, Chih-Ting Sun, Zi-Kuan Li, Bo-Sen Chang +1 more | 2023-10-03 |
| 11762302 | Integrated circuit overlay test patterns and method thereof | Bo-Sen Chang, Yueh-Yi Chen, Chih-Ting Sun, Ying-Jung Chen, Kung-Cheng Lin +1 more | 2023-09-19 |
| 11309307 | Integrated circuit filler and method thereof | Molly Chang, Ya-Wen Tseng, Chih-Ting Sun, Zi-Kuan Li, Bo-Sen Chang +1 more | 2022-04-19 |
| 11016398 | Integrated circuit overlay test patterns and method thereof | Bo-Sen Chang, Yueh-Yi Chen, Chih-Ting Sun, Ying-Jung Chen, Kung-Cheng Lin +1 more | 2021-05-25 |
| 10679980 | Integrated circuit filler and method thereof | Molly Chang, Ya-Wen Tseng, Chih-Ting Sun, Zi-Kuan Li, Bo-Sen Chang +1 more | 2020-06-09 |
| 10388645 | Integrated circuit filler and method thereof | Molly Chang, Ya-Wen Tseng, Chih-Ting Sun, Zi-Kuan Li, Bo-Sen Chang +1 more | 2019-08-20 |
| 10283496 | Integrated circuit filler and method thereof | Molly Chang, Ya-Wen Tseng, Chih-Ting Sun, Zi-Kuan Li, Bo-Sen Chang +1 more | 2019-05-07 |
| 10161965 | Method of test probe alignment control | Jui-Long Chen, Chien-Chih Liao, Chin-Hsiang Lin, Hui-Yun Chao, Jong-I Mou +1 more | 2018-12-25 |
| 9995770 | Multidirectional semiconductor arrangement testing | Huan Chi Tseng, Kuo-Chuan Chang, Yuan-Yao Chang, Chien-Chang Lee | 2018-06-12 |
| 9000798 | Method of test probe alignment control | Jui-Long Chen, Chien-Chih Liao, Hui-Yun Chao, Ta-Yung Lee, Jong-I Mou +1 more | 2015-04-07 |
| 7934173 | Reverse dummy insertion algorithm | Jiing-Shin Shyu | 2011-04-26 |
| 7825678 | Test pad design for reducing the effect of contact resistances | Yih-Yuh Doong, Chien-Chang Lee, Chih-Chieh Shao | 2010-11-02 |
| 7782073 | High accuracy and universal on-chip switch matrix testline | Kuo-Tsai Li, Shien-Yang Wu | 2010-08-24 |
| 6323097 | Electrical overlay/spacing monitor method using a ladder resistor | Shien-Yang Wu, Konrad Young | 2001-11-27 |