Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406130 | Geometric mask rule check with favorable and unfavorable zones | Shih-Ming Chang, Shinn-Sheng Yu, Ping-Chieh Wu | 2025-09-02 |
| 12019974 | Geometric mask rule check with favorable and unfavorable zones | Shih-Ming Chang, Shinn-Sheng Yu, Ping-Chieh Wu | 2024-06-25 |
| 11841619 | Method for mask data synthesis with wafer target adjustment | Hsu-Ting Huang, Tung-Chin Wu, Shih-Hsiang Lo, Chih-Ming Lai, Ru-Gun Liu +1 more | 2023-12-12 |
| 11764882 | Pre-conditional calibration for third order intermodulation distortion (IMD3) cancellation | Sai-Wang Tam, Alden C. Wong, Weiwei Xu, Yui Lin, Sridhar Reddy Narravula +1 more | 2023-09-19 |
| 11714951 | Geometric mask rule check with favorable and unfavorable zones | Shih-Ming Chang, Shinn-Sheng Yu, Ping-Chieh Wu | 2023-08-01 |
| 11646228 | Stealth dicing method including filamentation and apparatus thereof | Heping Zeng, Shuai Yuan, Yingsheng Du, Hui Xu, Yuan Nie +3 more | 2023-05-09 |
| 11374615 | Third order intermodulation distortion cancellation | Sai-Wang Tam, Alden C. Wong, Weiwei Xu, Yui Lin, Sridhar Reddy Narravula +2 more | 2022-06-28 |
| 11092899 | Method for mask data synthesis with wafer target adjustment | Hsu-Ting Huang, Tung-Chin Wu, Shih-Hsiang Lo, Chih-Ming Lai, Ru-Gun Liu +1 more | 2021-08-17 |
| 9495507 | Method for integrated circuit mask patterning | Lun Hsieh, Pi-Tsung Chen, Shuo-Yen Chou, Ru-Gun Liu | 2016-11-15 |
| 9256709 | Method for integrated circuit mask patterning | Lun Hsieh, Pi-Tsung Chen, Shuo-Yen Chou, Ru-Gun Liu | 2016-02-09 |