Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10096544 | Semiconductor interconnect structure | Chih-Ming Lai, Wen-Chun Huang, Ru-Gun Liu | 2018-10-09 |
| 9495507 | Method for integrated circuit mask patterning | Jue-Chin Yu, Lun Hsieh, Shuo-Yen Chou, Ru-Gun Liu | 2016-11-15 |
| 9256709 | Method for integrated circuit mask patterning | Jue-Chin Yu, Lun Hsieh, Shuo-Yen Chou, Ru-Gun Liu | 2016-02-09 |
| 8943445 | Method of merging color sets of layout | Ming-Hui Chih, Ken-Hsien Hsieh, Wei-Long Wang, Wen-Chun Huang, Ru-Gun Liu +4 more | 2015-01-27 |
| 8631379 | Decomposing integrated circuit layout | Ming-Hui Chih, Ken-Hsien Hsieh, Wei-Long Wang, Wen-Chun Huang, Ru-Gun Liu +4 more | 2014-01-14 |
| 8084328 | Semiconductor device including I/O oxide nitrided core oxide on substrate | Zhen-Cheng Wu, Yung-Cheng Lu, Ying-Tsung Chen | 2011-12-27 |
| 7834405 | Semiconductor device including I/O oxide and nitrided core oxide on substrate | Zhen-Cheng Wu, Yung-Cheng Lu, Ying-Tsung Chen | 2010-11-16 |
| 7456093 | Method for improving a semiconductor device delamination resistance | Keng-Chu Lin, Hui-Lin Chang, Lih-Ping Li, Tien-I Bao, Yung-Cheng Lu +1 more | 2008-11-25 |
| 7312531 | Semiconductor device and fabrication method thereof | Hui-Lin Chang, Yung-Cheng Lu, Chung-Chi Ko, Shau-Lin Shue, Chien-Hsueh Shih +2 more | 2007-12-25 |
| 7247571 | Method for planarizing semiconductor structures | Ying-Tsung Chen, Yung-Cheng Lu, Zhen-Cheng Wu | 2007-07-24 |
| 7217648 | Post-ESL porogen burn-out for copper ELK integration | Yung-Cheng Lu, Ying-Tsung Chen, Zhen-Cheng Wu | 2007-05-15 |