Issued Patents All Time
Showing 51–75 of 391 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11102913 | Heat dissipating assembly and main board module | Yung-Shun Kao, Tzu-Hsiang Huang | 2021-08-24 |
| 11098844 | Wall mount assembly | Yu-Chi Peng | 2021-08-24 |
| 11092899 | Method for mask data synthesis with wafer target adjustment | Hsu-Ting Huang, Tung-Chin Wu, Shih-Hsiang Lo, Jue-Chin Yu, Ru-Gun Liu +1 more | 2021-08-17 |
| 11087994 | Via connection to a partially filled trench | Shih-Ming Chang, Ru-Gun Liu, Tsai-Sheng Gau, Chung-Ju Lee, Tien-I Bao +1 more | 2021-08-10 |
| 11088092 | Via rail solution for high power electromigration | Kam-Tou Sio, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Chi-Yeh Yu +3 more | 2021-08-10 |
| 11089684 | Motherboard module and electronic device | Chung-Wei Chiang, Tzu-Hsiang Huang, Yung-Shun Kao | 2021-08-10 |
| 11080454 | Integrated circuit, system, and method of forming the same | Shih-Wei Peng, Jiann-Tyng Tzeng | 2021-08-03 |
| 11063005 | Via rail solution for high power electromigration | Kam-Tou Sio, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Chi-Yeh Yu +3 more | 2021-07-13 |
| 11043426 | Dummy MOL removal for performance enhancement | Hui-Ting Yang, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng +4 more | 2021-06-22 |
| 11024580 | Random cut patterning | Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2021-06-01 |
| 11024579 | Dual power structure with connection pins | Shih-Wei Peng, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng +3 more | 2021-06-01 |
| 11018157 | Local interconnect structure | Chih-Liang Chen, Cheng-Chi Chuang, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang +5 more | 2021-05-25 |
| 11004855 | Buried metal track and methods forming same | Pochun Wang, Ting-Wei Chiang, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu +6 more | 2021-05-11 |
| 11004738 | Capacitance reduction by metal cut design | Yi-Hsiung Lin, Yu-Xuan Huang, Ru-Gun Liu, Shang-Wen Chang, Yi-Hsun Chiu | 2021-05-11 |
| 11004729 | Method of manufacturing semiconductor devices | Ru-Gun Liu, Chin-Hsiang Lin, Wei-Liang Lin, Yung-Sung Yen | 2021-05-11 |
| 10991583 | Self aligned litho etch process patterning method | Chih-Min HSIAO, Chien-Wen Lai, Shih-Chun Huang, Yung-Sung Yen, Ru-Gun Liu | 2021-04-27 |
| 10978439 | Method and system of manufacturing conductors and semiconductor device which includes conductors | Kam-Tou Sio, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Ko-Bin Kao +2 more | 2021-04-13 |
| 10977421 | System for and method of manufacturing an integrated circuit | Wei-Cheng Lin, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio +3 more | 2021-04-13 |
| 10971363 | Method for forming semiconductor device structure | Shih-Ming Chang, Wei-Liang Lin, Chin-Yuan Tseng, Ru-Gun Liu | 2021-04-06 |
| 10950456 | High-density semiconductor device | Lei-Chun Chou, Chih-Liang Chen, Charles Chew-Yuen Young, Chin-Yuan Tseng, Hsin-Chih Chen +6 more | 2021-03-16 |
| 10930505 | Methods for integrated circuit design and fabrication | Tsong-Hua Ou, Ken-Hsien Hsieh, Shih-Ming Chang, Wen-Chun Huang, Ru-Gun Liu +1 more | 2021-02-23 |
| 10895007 | Evaporation apparatus and calibration method thereof | Yu-Lin Hsu, Chien-Hung Lin, Kuo-Hsin Huang, Chao-Feng Sung, Hung-Yi Chang | 2021-01-19 |
| 10878161 | Method and structure to reduce cell width in integrated circuits | Shih-Wei Peng, Jiann-Tyng Tzeng, Wei-Cheng Lin | 2020-12-29 |
| 10878162 | Metal with buried power for increased IC device density | Shih-Wei Peng, Hui-Ting Yang, Jiann-Tyng Tzeng, Wei-Cheng Lin | 2020-12-29 |
| 10879120 | Self aligned via and method for fabricating the same | Chih-Liang Chen, Cheng-Chi Chuang, Chia-Tien Wu, Charles Chew-Yuen Young, Jiann-Tyng Tzeng +4 more | 2020-12-29 |