Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9678529 | Efficiency-based clock frequency adjustment | Marcin Hlond | 2017-06-13 |
| 9141165 | Method and system for controlling clock frequency for active power management | Hlond Marcin | 2015-09-22 |
| 8725999 | Booting an integrated circuit | Stephen Felix | 2014-05-13 |
| 8589602 | Data transfer engine with delay circuitry for blocking transfers | Andrew Bond, Coleman Hegarty | 2013-11-19 |
| 8341451 | Clock configuration | Jon Mangnall | 2012-12-25 |
| 8024557 | Booting an integrated circuit | Stephen Felix | 2011-09-20 |
| 7996581 | DMA engine | Andrew Bond, Colman Hegarty | 2011-08-09 |
| 7890753 | Secure mode for processors supporting MMU and interrupts | Franck Dahan, Christian Roussel, Alain Chateau | 2011-02-15 |
| 7237081 | Secure mode for processors supporting interrupts | Franck Dahan, Christian Roussel, Alain Chateau | 2007-06-26 |
| 7120771 | Secure mode for processors supporting MMU | Franck Dahan, Christian Roussel, Alain Chateau | 2006-10-10 |
| 6989702 | Retention register with normal functionality independent of retention power supply | Uming Ko, David B. Scott, Sumanth Katte Gururajarao, Hugh Mair, Franck Dahan | 2006-01-24 |
| 6781411 | Flip flop with reduced leakage current | Donald E. Steiss, Clive Bittlestone, Christopher Michael Barr | 2004-08-24 |
| 5978908 | Computer instruction supply | Richard Roy Grisenthwaite | 1999-11-02 |
| 5946705 | Avoidance of cache synonyms | Richard Roy Grisenthwaite | 1999-08-31 |
| 5873115 | Cache memory | Richard Roy Grisenthwaite | 1999-02-16 |
| 5867698 | Apparatus and method for accessing a branch target buffer | Richard Roy Grisenthwaite | 1999-02-02 |