Issued Patents All Time
Showing 25 most recent of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11794627 | Folding camping apparatus | — | 2023-10-24 |
| 10978353 | High mobility transistors | Manoj Mehrotra, Charles Frank Machala, III, Hiroaki Niimi | 2021-04-13 |
| 10163725 | High mobility transistors | Manoj Mehrotra, Charles Frank Machala, III, Hiroaki Niimi | 2018-12-25 |
| 10026815 | Ultrashallow emitter formation using ALD and high temperature short time annealing | Hiroshi Yasuda | 2018-07-17 |
| 9929714 | Temperature compensated bulk acoustic wave resonator with a high coupling coefficient | Stuart M. Jacobsen, Maria Wang, Ricky Alan Jackson, Nicholas Stephen Dellas, Django Trombley | 2018-03-27 |
| 9805986 | High mobility transistors | Hiroaki Niimi, Manoj Mehrotra | 2017-10-31 |
| 9496262 | High mobility transistors | Manoj Mehrotra, Charles Frank Machala, III, Hiroaki Niimi | 2016-11-15 |
| 9396948 | Layer transfer of silicon onto III-nitride material for heterogenous integration | Naveen Tipirneni, Sameer Pendharkar | 2016-07-19 |
| 9324717 | High mobility transistors | Hiroaki Niimi, Manoj Mehrotra | 2016-04-26 |
| 9053966 | Integrated circuits with aligned (100) NMOS and (110) PMOS finFET sidewall channels | Weize Xiong, Cloves Rinn Cleavelin, Angelo Pinto | 2015-06-09 |
| 8872220 | Integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels | Weize Xiong, Cloves Rinn Cleavelin, Angelo Pinto | 2014-10-28 |
| 8846487 | Reduction of STI corner defects during SPE in semiconductor device fabrication using DSB substrate and hot technology | Angelo Pinto, Periannan Chidambaram | 2014-09-30 |
| 8835263 | Formation of a selective carbon-doped epitaxial cap layer on selective epitaxial SiGe | Johan W. Weijtmans, Jiong-Ping Lu | 2014-09-16 |
| 8828835 | Ultrashallow emitter formation using ALD and high temperature short time annealing | Hiroshi Yasuda | 2014-09-09 |
| 8759198 | Accelerated furnace ramp rates for reduced slip | Bradley David Sucher | 2014-06-24 |
| 8410519 | Integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels | Weize Xiong, Cloves Rinn Cleavelin, Angelo Pinto | 2013-04-02 |
| 8138035 | Method for forming integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels | Weize Xiong, Cloves Rinn Cleavelin, Angelo Pinto | 2012-03-20 |
| 8053322 | Epitaxial deposition-based processes for reducing gate dielectric thinning at trench edges and integrated circuits therefrom | Vladimir F. Drobny, Amitava Chatterjee, Phillipp Steinmann | 2011-11-08 |
| 7897994 | Method of making (100) NMOS and (110) PMOS sidewall surface on the same fin orientation for multiple gate MOSFET with DSB substrate | Weize Xiong, Cloves Rinn Cleavelin, Angelo Pinto | 2011-03-01 |
| 7767510 | Semiconductor device made by the method of producing hybrid orientnation (100) strained silicon with (110) silicon | Angelo Pinto | 2010-08-03 |
| 7443007 | Trench isolation structure having an implanted buffer layer | Mark S. Rodder | 2008-10-28 |
| 7371658 | Trench isolation structure and a method of manufacture therefor | Mark S. Rodder | 2008-05-13 |
| 7163878 | Ultra-shallow arsenic junction formation in silicon germanium | Puneet Kohli, Mark S. Rodder, Amitabh Jain | 2007-01-16 |
| 7160782 | Method of manufacture for a trench isolation structure having an implanted buffer layer | Mark S. Rodder | 2007-01-09 |
| 6699745 | Capacitor and memory structure and method | Aditi Banerjee, Darius Crenshaw | 2004-03-02 |