Issued Patents All Time
Showing 26–50 of 230 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11910587 | Memory circuit having SRAM memory cells and method for forming a SRAM memory cell structure | Hidehiro Fujiwara, Yi-Hsin Nien | 2024-02-20 |
| 11869623 | Latch type sense amplifier | Hua-Hsin Yu, Cheng Hung Lee, Hau-Tai Shieh | 2024-01-09 |
| 11854943 | Memory macro including through-silicon via | Hidehiro Fujiwara, Tze-Chiang Huang, Hong-Chen Cheng, Yen-Huei Chen, Jonathan Tsung-Yung Chang +2 more | 2023-12-26 |
| 11854970 | Reducing internal node loading in combination circuits | Chien-Yuan Chen, Cheng Hung Lee, Hau-Tai Shieh, Kao-Cheng Lin, Wei Min Chan | 2023-12-26 |
| 11848047 | Pre-charging bit lines through charge-sharing | Mahmut Sinangil, Chiting Cheng, Tsung-Yung Chang | 2023-12-19 |
| 11830544 | Write assist for a memory device and methods of forming the same | Sahil Preet Singh, Yen-Huei Chen | 2023-11-28 |
| 11830543 | Memory computation circuit | Yen-Huei Chen, Hidehiro Fujiwara, Jonathan Tsung-Yung Chang | 2023-11-28 |
| 11817144 | Arrangements of memory devices and methods of operating the memory devices | Chien-Yuan Chen, Hau-Tai Shieh, Cheng Hung Lee | 2023-11-14 |
| 11798632 | Floating data line circuit and method | Manish Arora, Yen-Huei Chen, Nikhil Puri, Yu-Hao Hsu | 2023-10-24 |
| 11783890 | Semiconductor device including distributed write driving arrangement | Hidehiro Fujiwara, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen | 2023-10-10 |
| 11778802 | SRAM cell word line structure with reduced RC effects | Hidehiro Fujiwara, Wei Min Chan, Chih-Yu Lin, Yen-Huei Chen | 2023-10-03 |
| 11763882 | Low voltage memory device | Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Jonathan Tsung-Yung Chang | 2023-09-19 |
| 11728789 | Voltage supply selection circuit | Chia-Chen Kuo, Yangsyu Lin, Yu-Hao Hsu, Cheng Hung Lee, Jonathan Tsung-Yung Chang | 2023-08-15 |
| 11726539 | Power management circuit, system-on-chip device, and method of power management | Chia-Chen Kuo, Yangsyu Lin, Yu-Hao Hsu, Cheng Hung Lee | 2023-08-15 |
| 11723195 | Semiconductor device having an inter-layer via (ILV), and method of making same | Tsung-Hsien Huang, Hong-Chen Cheng, Cheng Hung Lee | 2023-08-08 |
| 11714570 | Computing-in-memory device and method | Jonathan Tsung-Yung Chang, Hidehiro Fujiwara, Yen-Huei Chen, Yih Wang, Haruki Mori | 2023-08-01 |
| 11715505 | Memory circuit and method of operating the same | Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Fu-An Wu, He-Zhou WAN +1 more | 2023-08-01 |
| 11675505 | Configurable memory storage system | Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu +6 more | 2023-06-13 |
| 11670362 | Sub-word line driver placement for memory device | Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh | 2023-06-06 |
| 11651804 | Memory macro and method of operating the same | Chien-Kuo Su, Chiting Cheng, Pankaj Aggarwal, Yen-Huei Chen, Cheng Hung Lee +2 more | 2023-05-16 |
| 11637108 | Memory array circuit and method of manufacturing same | Hidehiro Fujiwara, Chih-Yu Lin, Hsien-Yu Pan, Yasutoshi Okuno, Yen-Huei Chen | 2023-04-25 |
| 11610628 | Static random access memory | Wei-Cheng Wu, Ping-Wei Wang, Wei Min Chan, Yen-Huei Chen | 2023-03-21 |
| 11579648 | Voltage regulator with power rail tracking | Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu +2 more | 2023-02-14 |
| 11574098 | Method for eliminating false paths of a circuit unit to be implemented using a system | Chun-Jiun Dai, Wei Min Chan, Yen-Huei Chen | 2023-02-07 |
| 11562946 | Memory macro including through-silicon via | Hidehiro Fujiwara, Tze-Chiang Huang, Hong-Chen Cheng, Yen-Huei Chen, Jonathan Tsung-Yung Chang +2 more | 2023-01-24 |