Issued Patents All Time
Showing 76–100 of 230 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11011238 | Floating data line circuits and methods | Manish Arora, Yen-Huei Chen, Nikhil Puri, Yu-Hao Hsu | 2021-05-18 |
| 10991420 | Semiconductor device including distributed write driving arrangement and method of operating same | Hidehiro Fujiwara, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen | 2021-04-27 |
| 10971217 | SRAM cell for interleaved wordline scheme | Hidehiro Fujiwara, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil | 2021-04-06 |
| 10971220 | Write assist for a memory device and methods of forming the same | Sahil Preet Singh, Yen-Huei Chen | 2021-04-06 |
| 10964683 | Memory array circuit and method of manufacturing the same | Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Sahil Preet Singh | 2021-03-30 |
| 10964389 | Memory cell | Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Chien-Chen Lin | 2021-03-30 |
| 10964355 | Memory device with strap cells | Jonathan Tsung-Yung Chang, Cheng Hung Lee, Chi-Ting Cheng, Jhon Jhy Liaw, Yen-Huei Chen | 2021-03-30 |
| 10950296 | Latch circuit formed from bit cell | Hua-Hsin Yu, Cheng Hung Lee, Hau-Tai Shieh | 2021-03-16 |
| 10949100 | Configurable memory storage system | Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu +6 more | 2021-03-16 |
| 10878890 | Operation assist circuit, memory device and operation assist method | Chien-Yuan Chen, Cheng Hung Lee, Hau-Tai Shieh | 2020-12-29 |
| 10854282 | Memory read stability enhancement with short segmented bit line architecture | Mahmut Sinangil, Hidehiro Fujiwara, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh | 2020-12-01 |
| 10847217 | Pre-charging bit lines through charge-sharing | Mahmut Sinangil, Chiting Cheng, Tsung-Yung Chang | 2020-11-24 |
| 10847214 | Low voltage bit-cell | Mahmut Sinangil, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Yen-Ting Lin | 2020-11-24 |
| 10839894 | Memory computation circuit and method | Yen-Huei Chen, Hidehiro Fujiwara, Jonathan Tsung-Yung Chang | 2020-11-17 |
| 10832765 | Variation tolerant read assist circuit for SRAM | Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Sahil Preet Singh | 2020-11-10 |
| 10803928 | Low voltage memory device | Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Jonathan Tsung-Yung Chang | 2020-10-13 |
| 10783955 | Memory circuit having shared word line | Hidehiro Fujiwara, Li-Wen Wang, Yen-Huei Chen | 2020-09-22 |
| 10778198 | Level shifter | Chien-Yuan Chen, Cheng Hung Lee, Hau-Tai Shieh | 2020-09-15 |
| 10770131 | SRAM cell for interleaved wordline scheme | Hidehiro Fujiwara, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil | 2020-09-08 |
| 10755768 | Semiconductor device including distributed write driving arrangement and method of operating same | Hidehiro Fujiwara, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen | 2020-08-25 |
| 10734066 | Static random access memory with write assist circuit | Hidehiro Fujiwara, Chih-Yu Lin, Sahil Preet Singh, Hsien-Yu Pan, Yen-Huei Chen | 2020-08-04 |
| 10714181 | Memory cell | Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Chien-Chen Lin | 2020-07-14 |
| 10685704 | Static random access memory circuit | Wei-Cheng Wu, Wei Min Chan, Yen-Huei Chen, Ping-Wei Wang | 2020-06-16 |
| 10685686 | Power switch control for dual power supply | Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Jonathan Tsung-Yung Chang, Yu-Hao Hsu | 2020-06-16 |
| 10672776 | Memory circuit having resistive device coupled with supply voltage line | Yen-Huei Chen, Chih-Yu Lin, Jonathan Tsung-Yung Chang, Wei-Cheng Wu | 2020-06-02 |