Issued Patents All Time
Showing 126–150 of 230 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10083739 | Three-dimensional three-port bit cell and method of assembling same | Tzu-Kuei Lin, Yen-Huei Chen, Ching-Wei Wu | 2018-09-25 |
| 10062419 | Digtial circuit structures | Hidehiro Fujiwara, Chih-Yu Lin, Wei-Cheng Wu, Yen-Huei Chen | 2018-08-28 |
| 10024906 | Timing skew characterization apparatus and method | Chao Kai Chuang, Yen-Chien Lai | 2018-07-17 |
| 9997219 | Memory macro and method of operating the same | Chien-Kuo Su, Cheng Hung Lee, Chiting Cheng, Jonathan Tsung-Yung Chang, Yen-Huei Chen +2 more | 2018-06-12 |
| 9979399 | Level shifter | Chien-Yuan Chen, Cheng Hung Lee, Hau-Tai Shieh, Che-Ju Yeh | 2018-05-22 |
| 9959916 | Dual rail memory, memory macro and associated hybrid power supply method | Jonathan Tsung-Yung Chang, Chiting Cheng, Cheng Hung Lee, Michael Patrick Clinton | 2018-05-01 |
| 9922701 | Pre-charging bit lines through charge-sharing | Mahmut Sinangil, Chiting Cheng, Tsung-Yung Chang | 2018-03-20 |
| 9922700 | Memory read stability enhancement with short segmented bit line architecture | Mahmut Sinangil, Hidehiro Fujiwara, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh | 2018-03-20 |
| 9886996 | SRAM cell for interleaved wordline scheme | Hidehiro Fujiwara, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil | 2018-02-06 |
| 9865605 | Memory circuit having resistive device coupled with supply voltage line | Yen-Huei Chen, Chih-Yu Lin, Jonathan Tsung-Yung Chang, Wei-Cheng Wu | 2018-01-09 |
| 9853035 | Layout scheme and method for forming device cells in semiconductor devices | Hsien-Yu Pan, Jung-Hsuan Chen, Shao-Yu Chou, Yen-Huei Chen | 2017-12-26 |
| 9842627 | Memory device with strap cells | Jonathan Tsung-Yung Chang, Cheng Hung Lee, Chi-Ting Cheng, Jhon Jhy Liaw, Yen-Huei Chen | 2017-12-12 |
| 9837130 | Digtial circuit structures to control leakage current | Hidehiro Fujiwara, Chih-Yu Lin, Wei-Cheng Wu, Yen-Huei Chen | 2017-12-05 |
| 9824729 | Memory macro and method of operating the same | Chien-Kuo Su, Cheng Hung Lee, Chiting Cheng, Jonathan Tsung-Yung Chang, Yen-Huei Chen +2 more | 2017-11-21 |
| 9762216 | Level shifter circuit using boosting circuit | Mahmut Sinangil, Hsin-Hsin Ko, Chiting Cheng, Yen-Huei Chen, Jonathan Tsung-Yung Chang | 2017-09-12 |
| 9741429 | Memory with write assist circuit | Yen-Huei Chen, Hidehiro Fujiwara, Jonathan Tsung-Yung Chang | 2017-08-22 |
| 9704565 | Method of using a static random access memory | Wei-Cheng Wu, Wei Min Chan, Yen-Huei Chen, Ping-Wei Wang | 2017-07-11 |
| 9685224 | Memory with bit line control | Chen-Lin Yang, Cheng Hung Lee, Kao-Cheng Lin, Jonathan Tsung-Yung Chang, Yu-Hao Hsu | 2017-06-20 |
| 9685223 | Voltage controller | Wei-Cheng Wu, Wei Min Chan, Yen-Huei Chen | 2017-06-20 |
| 9666253 | Dual rail memory, memory macro and associated hybrid power supply method | Jonathan Tsung-Yung Chang, Chiting Cheng, Cheng Hung Lee, Michael Patrick Clinton | 2017-05-30 |
| 9659620 | Memory device with self-boosted mechanism | Yen-Huei Chen, Chih-Yu Lin, Jonathan Tsung-Yung Chang, Wei-Cheng Wu | 2017-05-23 |
| 9640251 | Multi-port memory cell | Hidehiro Fujiwara, Kao-Cheng Lin, Yen-Huei Chen | 2017-05-02 |
| 9607683 | Emulator for imulating an operation of a SRAM | Hidehiro Fujiwara, Yen-Huei Chen | 2017-03-28 |
| 9601162 | Memory devices with strap cells | Jonathan Tsung-Yung Chang, Cheng Hung Lee, Chi-Ting Cheng, Jhon Jhy Liaw, Yen-Huei Chen | 2017-03-21 |
| 9589885 | Device having multiple-layer pins in memory MUX1 layout | Jung-Hsuan Chen, Chien-Chi TIEN, Ching-Wei Wu, Jui-Che Tsai, Hong-Chen Cheng +1 more | 2017-03-07 |