Issued Patents All Time
Showing 176–200 of 230 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8958232 | Method and apparatus for read assist to compensate for weak bit | Jonathan Tsung-Yung Chang, Cheng Hung Lee, Chung-Cheng Chou, Bin-Hau Lo | 2015-02-17 |
| 8942053 | Generating and amplifying differential signals | Chung-Ji Lu, Cheng Hung Lee, Derek C. Tao, Annie-Li-Keow Lum, Hong-Chen Cheng | 2015-01-27 |
| 8928113 | Layout scheme and method for forming device cells in semiconductor devices | Hsien-Yu Pan, Jung-Hsuan Chen, Shao-Yu Chou, Yen-Huei Chen | 2015-01-06 |
| 8907681 | Timing skew characterization apparatus and method | Chao Kai Chuang, Yen-Chien Lai | 2014-12-09 |
| 8792292 | Providing row redundancy to solve vertical twin bit failures | Hong-Chen Cheng, Jung-Ping Yang, Chung-Ji Lu, Derek C. Tao, Cheng Hung Lee | 2014-07-29 |
| 8773930 | Built-in test circuit and method | Tzu-Kuei Lin, Yen-Huei Chen, Fang Jao | 2014-07-08 |
| 8767493 | SRAM differential voltage sensing apparatus | Yen-Huei Chen, Kun-Hsi Li, Shao-Yu Chou, Wei Min Chan | 2014-07-01 |
| 8723265 | Semiconductor structure with dummy polysilicon lines | Yen-Huei Chen, Wei Min Chan, Shao-Yu Chou | 2014-05-13 |
| 8713491 | Pre-colored methodology of multiple patterning | Yen-Huei Chen, Jonathan Tsung-Yung Chang | 2014-04-29 |
| 8693265 | Data inversion for dual-port memory | Tzu-Kuei Lin, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Jhon Jhy Liaw | 2014-04-08 |
| 8675439 | Bit line voltage bias for low power memory design | Hong-Chen Cheng, Jung-Ping Yang, Chiting Cheng, Cheng Hung Lee, Sang H. Dong | 2014-03-18 |
| 8665654 | Memory edge cell | Hong-Chen Cheng, Ming-Yi Lee, Kuo-Hua Pan, Jung-Hsuan Chen, Li-Chun Tien +1 more | 2014-03-04 |
| 8610236 | Edge devices layout for improved performance | Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Li-Chun Tien | 2013-12-17 |
| 8601411 | Pre-colored methodology of multiple patterning | Yen-Huei Chen, Wei Min Chan, Jonathan Tsung-Yung Chang | 2013-12-03 |
| 8576655 | Semiconductor memories | Wei Min Chan, Yen-Huei Chen, Jihi-Yu Lin, Hsien-Yu Pan | 2013-11-05 |
| 8559251 | Memory circuit and method of writing datum to memory circuit | Chih-Yu Lin, Wei Min Chan, Yen-Huei Chen, Jonathan Tsung-Yung Chang | 2013-10-15 |
| 8553448 | SRAM cells, memory circuits, systems, and fabrication methods thereof | Chen-Hung LEE | 2013-10-08 |
| 8488395 | Keepers, integrated circuits, and systems thereof | Cheng Hung Lee, Ching-Wei Wu, Bin Sheng | 2013-07-16 |
| 8482990 | Memory edge cell | Hong-Chen Cheng, Ming-Yi Lee, Kuo-Hua Pan, Jung-Hsuan Chen, Li-Chun Tien +1 more | 2013-07-09 |
| 8455354 | Layouts of POLY cut openings overlapping active regions | Jung-Hsuan Chen, Yen-Huei Chen, Li-Chun Tien | 2013-06-04 |
| 8427888 | Word-line driver using level shifter at local control circuit | Chung-Ji Lu, Lee Cheng Hung, Hsu-Shun Chen, Hong-Chen Cheng, Chung-Yi Wu +1 more | 2013-04-23 |
| 8406028 | Word line layout for semiconductor memory | Tzu-Kuei Lin, Yen-Huei Chen, Ping-Wei Wang, Huai-Ying Huang | 2013-03-26 |
| 8406075 | Ultra-low leakage memory architecture | Cheng Hung Lee | 2013-03-26 |
| 8395950 | Memory device having a clock skew generator | Tzu-Kuei Lin, Shao-Yu Chou, Ching-Wei Wu | 2013-03-12 |
| 8363454 | SRAM bit cell | Ping-Wei Wang, Yen-Huei Chen, Jihi-Yu Lin, Shao-Yu Chou | 2013-01-29 |