Issued Patents All Time
Showing 1,476–1,500 of 1,955 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8912651 | Package-on-package (PoP) structure including stud bulbs and method | Mirng-Ji Lii, Chung-Shi Liu, Ming-Da Cheng | 2014-12-16 |
| 8912602 | FinFETs and methods for forming the same | Yu-Rung Hsu, Chen-Nan Yeh | 2014-12-16 |
| 8901735 | Connector design for packaging integrated circuits | Ying-Ching Shih, Po-Hao Tsai, Chin-Fu Kao, Cheng-Lin Huang, Cheng-Chieh Hsieh +4 more | 2014-12-02 |
| 8900994 | Method for producing a protective structure | Shin-Puu Jeng, Wen-Chih Chiou, Fang Wen Tsai, Chen-Yu Tsai | 2014-12-02 |
| 8896127 | Via structure and via etching process of forming the same | Hung-Pin Chang, Wen-Chih Chiou | 2014-11-25 |
| 8896136 | Alignment mark and method of formation | Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai +4 more | 2014-11-25 |
| 8890274 | Interconnect structure for CIS flip-chip bonding and methods for forming the same | Yung Ching Chen, Chien-Hsun Lee, Mirng-Ji Lii | 2014-11-18 |
| 8883597 | Method of fabrication of a FinFET element | Cheng-Hung Chang, Chen-Nan Yeh, Chu-Yun Fu, Yu-Rang Hsu, Ding-Yuan Chen | 2014-11-11 |
| 8884431 | Packaging methods and structures for semiconductor devices | Chih-Wei Lin, Ming-Da Cheng, Wen-Hsiung Lu, Hsiu-Jen Lin, Bor-Ping Jang +7 more | 2014-11-11 |
| 8878182 | Probe pad design for 3DIC package yield analysis | Tzu-Yu Wang, Shin-Puu Jeng, Shang-Yun Hou, Hsien-Pin Hu, Wei-Cheng Wu +2 more | 2014-11-04 |
| 8878252 | III-V compound semiconductor epitaxy from a non-III-V substrate | Chia-Lin Yu, Ding-Yuan Chen, Wen-Chih Chiou | 2014-11-04 |
| 8871609 | Thin wafer handling structure and method | Kuo-Ching Hsu, Chen-Shien Chen, Ching-Wen Hsiao | 2014-10-28 |
| 8866301 | Package systems having interposers with interconnection structures | Yung-Chi Lin, Jing-Cheng Lin | 2014-10-21 |
| 8865521 | 3D semiconductor package interposer with die cavity | Shin-Puu Jeng, Kim Hong Chen, Shang-Yun Hou, Chao-Wen Shih, Cheng-Chieh Hsieh | 2014-10-21 |
| 8860208 | Heat spreader structures in scribe lines | Hsien-Wei Chen, Yu-Wen Liu, Jyh-Cherng Sheu, Hao-Yi Tsai, Shin-Puu Jeng +1 more | 2014-10-14 |
| 8853830 | System, structure, and method of manufacturing a semiconductor substrate stack | Hung-Pin Chang, Weng-Jin Wu, Wen-Chih Chiou | 2014-10-07 |
| 8846499 | Composite carrier structure | Ying-Ching Shih, Weng-Jin Wu, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng | 2014-09-30 |
| 8847388 | Bump with protection structure | Hung-Pin Chang, An-Jhih Su, Tsang-Jiuh Wu, Wen-Chih Chiou, Shin-Puu Jeng | 2014-09-30 |
| 8841773 | Multi-layer interconnect structure for stacked dies | Hung-Pin Chang, Chien-Ming Chiu, Tsang-Jiuh Wu, Shau-Lin Shue | 2014-09-23 |
| 8836127 | Interconnect with flexible dielectric layer | Ching-Yu Lo, Bo-Jiun Lin, Hai-Ching Chen, Tien-I Bao, Shau-Lin Shue | 2014-09-16 |
| 8835313 | Interconnect barrier structure and method | Wen-Chih Chiou, Tsang-Jiuh Wu | 2014-09-16 |
| 8835193 | Non-uniform alignment of wafer bumps with substrate solders | Hung-Jui Kuo, Chung-Shi Liu | 2014-09-16 |
| 8827695 | Wafer's ambiance control | Yi-Li Hsiao, Jean Wang, Ming-Che Ho, Chien Ling Hwang, Jui-Pin Hung | 2014-09-09 |
| 8829676 | Interconnect structure for wafer level package | Jing-Cheng Lin, Nai-Wei Liu, Jui-Pin Hung, Shin-Puu Jeng | 2014-09-09 |
| 8822293 | Self-aligned halo/pocket implantation for reducing leakage and source/drain resistance in MOS devices | Yihang Chiu, Shu-Tine Yang, Jyh-Cherng Sheu, Chu-Yun Fu, Cheng-Tung Lin | 2014-09-02 |