Issued Patents All Time
Showing 1,526–1,550 of 1,955 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8735273 | Forming wafer-level chip scale package structures with reduced number of seed layers | Wen-Hsiung Lu, Ming-Da Cheng, Chih-Wei Lin, Yi-Wen Wu, Hsiu-Jen Lin +2 more | 2014-05-27 |
| 8729703 | Schemes for forming barrier layers for copper in interconnect structures | Hai-Ching Chen, Tien-I Bao | 2014-05-20 |
| 8729706 | Semiconductor structure having a permeable hard mask layer sealing an air gap | Chung-Shi Liu | 2014-05-20 |
| 8722286 | Devices and methods for improved reflective electron beam lithography | Jaw-Jung Shin, Shy-Jay Lin, Burn Jeng Lin | 2014-05-13 |
| 8716858 | Bump structure with barrier layer on post-passivation interconnect | Chen-Fa Lu, Chung-Shi Liu, Mirng-Ji Lii | 2014-05-06 |
| 8716867 | Forming interconnect structures using pre-ink-printed sheets | Francis Ko, Chi-Chun Hsieh, Shang-Yun Hou, Wen-Chih Chiou, Shin-Puu Jeng | 2014-05-06 |
| 8716723 | Reflective layer between light-emitting diodes | Ding-Yuan Chen, Chia-Lin Yu, Wen-Chih Chiou | 2014-05-06 |
| 8710660 | Hybrid interconnect scheme including aluminum metal line in low-k dielectric | Tien-I Bao | 2014-04-29 |
| 8703539 | Multiple die packaging interposer structure and method | Mirng-Ji Lii, Hao-Yi Tsai, Jui-Pin Hung, Chien-Hsiun Lee, Kai-Chiang Wu | 2014-04-22 |
| 8698306 | Substrate contact opening | Jiun Yi Wu | 2014-04-15 |
| 8691706 | Reducing substrate warpage in semiconductor processing | Wen-Chih Chiou, Fang Wen Tsai, Kuang-Wei Cheng, Jiann Sheng Chang, Yi Chou Lai +1 more | 2014-04-08 |
| 8686474 | III-V compound semiconductor epitaxy from a non-III-V substrate | Ding-Yuan Chen, Wen-Chih Chiou, Chia-Lin Yu | 2014-04-01 |
| 8685798 | Methods for forming through vias | Tung-Liang Shao, Chih-Hang Tung, Hao-Yi Tsai, Mirng-Ji Lii, Da-Yuan Shih | 2014-04-01 |
| 8680647 | Packages with passive devices and methods of forming the same | Shang-Yun Hou, Der-Chyang Yeh, Shuo-Mao Chen, Chiung-Han Yeh, Yi-Jou Lin | 2014-03-25 |
| 8682466 | Automatic virtual metrology for semiconductor wafer result prediction | Francis Ko, Chih-Wei Lai, Kewei Zuo, Henry Lo, Jean Wang +2 more | 2014-03-25 |
| 8680682 | Barrier for through-silicon via | Wen-Chih Chiou, Weng-Jin Wu | 2014-03-25 |
| 8674513 | Interconnect structures for substrate | Wen-Chih Chiou, Shin-Puu Jeng, Tsang-Jiuh Wu | 2014-03-18 |
| 8669174 | Multi-die stacking using bumps with different sizes | Weng-Jin Wu, Ying-Ching Shih, Wen-Chih Chiou, Shin-Puu Jeng | 2014-03-11 |
| 8668131 | In-situ accuracy control in flux dipping | Yi-Li Hsiao, Chung-Shi Liu, Chien Ling Hwang | 2014-03-11 |
| 8664070 | High temperature gate replacement process | Chung-Shi Liu | 2014-03-04 |
| 8664040 | Exposing connectors in packages through selective treatment | Chung-Shi Liu, Chun-Cheng Lin, Meng-Tse Chen, Ming-Da Cheng | 2014-03-04 |
| 8664760 | Connector design for packaging integrated circuits | Shin-Puu Jeng, Shang-Yun Hou, Cheng-Chieh Hsieh, Kuo-Ching Hsu, Ying-Ching Shih +4 more | 2014-03-04 |
| 8664041 | Method for designing a package and substrate layout | Yu-Jen Tseng, Guan-Yu Chen, Sheng-Yu Wu, Mirng-Ji Lii, Chen-Shien Chen +1 more | 2014-03-04 |
| 8659033 | Light-emitting diode with textured substrate | Wen-Chih Chiou, Ding-Yuan Chen, Chia-Lin Yu, Hung-Ta Lin | 2014-02-25 |
| 8652260 | Apparatus for holding semiconductor wafers | Chien Ling Hwang | 2014-02-18 |