Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10910267 | Alignment marks in substrate having through-substrate via (TSV) | Hsin Chang, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng | 2021-02-02 |
| 10692764 | Alignment marks in substrate having through-substrate via (TSV) | Hsin Chang, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng | 2020-06-23 |
| 10163706 | Alignment marks in substrate having through-substrate via (TSV) | Hsin Chang, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng | 2018-12-25 |
| 9997497 | Through silicon via structure | Chen-Hua Yu, Shin-Puu Jeng, Wen-Chih Chiou, Chen-Yu Tsai | 2018-06-12 |
| 9633900 | Method for through silicon via structure | Chen-Hua Yu, Shin-Puu Jeng, Wen-Chih Chiou, Chen-Yu Tsai | 2017-04-25 |
| 9478480 | Alignment mark and method of formation | Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Weng-Jin Wu +4 more | 2016-10-25 |
| 9299676 | Through silicon via structure | Chen-Hua Yu, Shin-Puu Jeng, Wen-Chih Chiou, Chen-Yu Tsai | 2016-03-29 |
| 9099515 | Reconfigurable guide pin design for centering wafers having different sizes | Hsin Chang, Hsin-Yu Chen, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng +1 more | 2015-08-04 |
| 9093314 | Copper bump structures having sidewall protection layers | Jing-Cheng Lin, Ya-Hsi Hwung, Hsin-Yu Chen, Po-Hao Tsai, Yan-Fu Lin +2 more | 2015-07-28 |
| 8980706 | Double treatment on hard mask for gate N/P patterning | Matt Yeh, Chi-Chun Chen | 2015-03-17 |
| 8952506 | Through silicon via structure | Chen-Hua Yu, Shin-Puu Jeng, Wen-Chih Chiou, Chen-Yu Tsai | 2015-02-10 |
| 8928159 | Alignment marks in substrate having through-substrate via (TSV) | Hsin Chang, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng | 2015-01-06 |
| 8922004 | Copper bump structures having sidewall protection layers | Jing-Cheng Lin, Ya-Hsi Hwung, Hsin-Yu Chen, Po-Hao Tsai, Yan-Fu Lin +2 more | 2014-12-30 |
| 8900994 | Method for producing a protective structure | Chen-Hua Yu, Shin-Puu Jeng, Wen-Chih Chiou, Chen-Yu Tsai | 2014-12-02 |
| 8896136 | Alignment mark and method of formation | Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Weng-Jin Wu +4 more | 2014-11-25 |
| 8691706 | Reducing substrate warpage in semiconductor processing | Chen-Hua Yu, Wen-Chih Chiou, Kuang-Wei Cheng, Jiann Sheng Chang, Yi Chou Lai +1 more | 2014-04-08 |
| 8567837 | Reconfigurable guide pin design for centering wafers having different sizes | Hsin Chang, Hsin-Yu Chen, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng +1 more | 2013-10-29 |
| 8513107 | Replacement gate FinFET devices and methods for forming the same | Bor-Wen Chan | 2013-08-20 |
| 8048810 | Method for metal gate N/P patterning | Jim Huang, Shun Wu Lin, Li-Shiun Chen, Kuang-Yuan Hsu | 2011-11-01 |
| RE42514 | Extreme low-K dielectric film scheme for advanced interconnects | Kuan-Chen Wang, Keng-Chu Lin, Chih-Lung Lin, Shwang-Ming Jeng | 2011-07-05 |
| 7732344 | High selectivity etching process for metal gate N/P patterning | Matt Yeh, Ming Wang, Shun Wu Lin, Chi-Chun Chen, Zin-Chang Wei +1 more | 2010-06-08 |
| 7626245 | Extreme low-k dielectric film scheme for advanced interconnect | Kuan-Chen Wang, Keng-Chu Lin, Chih-Lung Lin, Shwang-Ming Jeng | 2009-12-01 |
| 7465676 | Method for forming dielectric film to improve adhesion of low-k film | I-I Chen, Zhen-Cheng Wu, Chih-Lung Lin, Tien-I Bao, Shwang-Ming Jeng +1 more | 2008-12-16 |
| 6953608 | Solution for FSG induced metal corrosion & metal peeling defects with extra bias liner and smooth RF bias ramp up | Pong-Hsiung Leu, Yu-Min Chang, Jo-Wei Chen, Wan-Cheng Yang, Chyi-Tsong Ni | 2005-10-11 |