Issued Patents All Time
Showing 176–200 of 215 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8664041 | Method for designing a package and substrate layout | Yu-Jen Tseng, Guan-Yu Chen, Sheng-Yu Wu, Chen-Hua Yu, Chen-Shien Chen +1 more | 2014-03-04 |
| 8643196 | Structure and method for bump to landing trace ratio | Chen-Hua Yu, Tin-Hao Kuo, Chen-Shien Chen, Sheng-Yu Wu, Yen-Liang Lin | 2014-02-04 |
| 8642393 | Package on package devices and methods of forming same | Chen-Hua Yu, Chien-Hsun Lee, Yung Ching Chen, Jiun Yi Wu | 2014-02-04 |
| 8618827 | Measurement of electrical and mechanical characteristics of low-K dielectric in a semiconductor device | Tung-Liang Shao, Shih-Wei Liang, Ying-Ju Chen, Ching-Jung Yang, Hsien-Wei Chen +2 more | 2013-12-31 |
| 8610267 | Reducing delamination between an underfill and a buffer layer in a bond structure | Ching-Jung Yang, Chang-Pin Huang, Tzuan-Horng Liu, Michael Shou-Ming Tong, Ying-Ju Chen +3 more | 2013-12-17 |
| 8581400 | Post-passivation interconnect structure | Shih-Wei Liang, Hsien-Wei Chen, Ying-Ju Chen, Tsung-Yuan Yu | 2013-11-12 |
| 8551813 | Wafer level IC assembly method | Chien-Hsiun Lee, Clinton Chao, Tjandra Winata Karta | 2013-10-08 |
| 8540136 | Methods for stud bump formation and apparatus for performing the same | Yeong-Jyh Lin, Hsin-Hung Liao, Chien Ling Hwang, Yi-Li Hsiao, Chung-Shi Liu +1 more | 2013-09-24 |
| 8524595 | Semiconductor package structures | Hsin-Hui Lee | 2013-09-03 |
| 8501613 | UBM etching methods for eliminating undercut | Yi-Yang Lei, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu | 2013-08-06 |
| 8476770 | Apparatus and methods for forming through vias | Tung-Liang Shao, Chih-Hang Tung, Chen-Hua Yu, Hao-Yi Tsai, Da-Yuan Shih | 2013-07-02 |
| 8409881 | Multi-project wafer and method of making same | William Cheng, Chen Yung Ching, Hsin-Hui Lee | 2013-04-02 |
| 8377816 | Method of forming electrical connections | Chung-Shi Liu, Shin-Puu Jeng, Chen-Hua Yu | 2013-02-19 |
| 8334170 | Method for stacking devices | Dean Wang, Chien-Hsiun Lee, Chen-Shien Chen, Clinton Chao, Tjandra Winata Karta | 2012-12-18 |
| 8247267 | Wafer level IC assembly method | Chien-Hsiun Lee, Clinton Chao, Tjandra Winata Karta | 2012-08-21 |
| 8169076 | Interconnect structures having lead-free solder bumps | Chien-Hsiun Lee, Chen-Hua Yu, Shin-Puu Jeng, Chin-Yu Ku | 2012-05-01 |
| 8049323 | Chip holder with wafer level redistribution layer | Chen-Shien Chen, Chao-Hsiang Yang, Jimmy Liang, Han-Liang Tseng, Tjandra Winata Karta +1 more | 2011-11-01 |
| 8039315 | Thermally enhanced wafer level package | Hsin-Hui Lee, Chien-Hsiun Lee | 2011-10-18 |
| 7952167 | Scribe line layout design | Hsin-Hui Lee, Shin-Puu Jeng, Shang-Yun Hou | 2011-05-31 |
| 7851272 | Multi-project wafer and method of making same | William Cheng, Chen Yung Ching, Hsin-Hui Lee | 2010-12-14 |
| 7851331 | Bonding structures and methods of forming bonding structures | Szu-Wei Lu, Chen-Shien Chen, Hua-Shu Wu, Jerry Tzou | 2010-12-14 |
| 7846769 | Stratified underfill method for an IC package | Szu-Wei Lu, Tjandra Winata Karta, Chien-Hsiun Lee | 2010-12-07 |
| 7842548 | Fixture for P-through silicon via assembly | Chien-Hsiun Lee, Chen-Shien Chen, Tjandra Winata Karta | 2010-11-30 |
| 7772691 | Thermally enhanced wafer level package | Hsin-Hui Lee, Chien-Hsiun Lee | 2010-08-10 |
| 7662665 | Method for fabricating a semiconductor package including stress relieving layer for flip chip packaging | Chen-Shien Chen, Kuo-Chin Chang, Szu-Wei Lu, Pei-Haw Tsao, Chung Yu Wang +1 more | 2010-02-16 |