Issued Patents All Time
Showing 1–25 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11935842 | Methods of manufacturing an integrated circuit having stress tuning layer | Shin-Puu Jeng, Szu-Wei Lu | 2024-03-19 |
| 11094646 | Methods of manufacturing an integrated circuit having stress tuning layer | Shin-Puu Jeng, Szu-Wei Lu | 2021-08-17 |
| 10269730 | Methods of manufacturing an integrated circuit having stress tuning layer | Shin-Puu Jeng, Szu-Wei Lu | 2019-04-23 |
| 9633954 | Methods of manufacturing an integrated circuit having stress tuning layer | Shin-Puu Jeng, Szu-Wei Lu | 2017-04-25 |
| 9275948 | Integrated circuit having stress tuning layer | Shin-Puu Jeng, Szu-Wei Lu | 2016-03-01 |
| 8945998 | Programmable semiconductor interposer for electronic package and method of forming | Chao-Shun Hsu, Mark Shane Peng | 2015-02-03 |
| 8704383 | Silicon-based thin substrate and packaging schemes | Szu-Wei Lu, Ann Luh, Tjandra Winata Karta, Jerry Tzou, Kuo-Chin Chang | 2014-04-22 |
| 8551813 | Wafer level IC assembly method | Chien-Hsiun Lee, Mirng-Ji Lii, Tjandra Winata Karta | 2013-10-08 |
| 8476735 | Programmable semiconductor interposer for electronic package and method of forming | Chao-Shun Hsu, Mark Shane Peng | 2013-07-02 |
| 8426256 | Method of forming stacked-die packages | C. W. Hsiao, Bo-I Lee, Tsung-Ding Wang, Kai-Ming Ching, Chen-Shien Chen +1 more | 2013-04-23 |
| 8367474 | Method of manufacturing integrated circuit having stress tuning layer | Shin-Puu Jeng, Szu-Wei Lu | 2013-02-05 |
| 8334170 | Method for stacking devices | Dean Wang, Chien-Hsiun Lee, Chen-Shien Chen, Mirng-Ji Lii, Tjandra Winata Karta | 2012-12-18 |
| 8322020 | Method for fabricating a semiconductor test probe card space transformer | Ming-Cheng Hsu | 2012-12-04 |
| 8247267 | Wafer level IC assembly method | Chien-Hsiun Lee, Mirng-Ji Lii, Tjandra Winata Karta | 2012-08-21 |
| 8232183 | Process and apparatus for wafer-level flip-chip assembly | Chien-Hsiun Lee, Ming-Chung Sung, Tjandra Winata Karta | 2012-07-31 |
| 8174129 | Silicon-based thin substrate and packaging schemes | Szu-Wei Lu, Ann Luh, Tjandra Winata Karta, Jerry Tzou, Kuo-Chin Chang | 2012-05-08 |
| 8146245 | Method for assembling a wafer level test probe card | Fei-Chieh Yang, Chun-Hsing Chen, Mill-Jer Wang, Sheng-Hsi Huang, Ming-Cheng Hsu | 2012-04-03 |
| 8033012 | Method for fabricating a semiconductor test probe card space transformer | Ming-Cheng Hsu | 2011-10-11 |
| 7977155 | Wafer-level flip-chip assembly methods | Chien-Hsiun Lee, Ming-Chung Sung, Tjandra Winata Karta | 2011-07-12 |
| 7880278 | Integrated circuit having stress tuning layer | Shin-Puu Jeng, Szu-Wei Lu | 2011-02-01 |
| 7812426 | TSV-enabled twisted pair | Mark Shane Peng, Chao-Shun Hsu | 2010-10-12 |
| 7804177 | Silicon-based thin substrate and packaging schemes | Szu-Wei Lu, Ann Luh, Tjandra Winata Karta, Jerry Tzou, Kuo-Chin Chang | 2010-09-28 |
| 7795735 | Methods for forming single dies with multi-layer interconnect structures and structures formed therefrom | Chao-Shun Hsu, Chen-Yao Tang, Mark Shane Peng | 2010-09-14 |
| 7750651 | Wafer level test probe card | Fei-Chieh Yang, Chun-Hsing Chen, Mill-Jer Wang, Sheng-Hsi Huang, Ming-Cheng Hsu | 2010-07-06 |
| 7696766 | Ultra-fine pitch probe card structure | Hsu Ming Cheng, Fa-Yuan Chang, Hua-Shu Wu | 2010-04-13 |