Issued Patents All Time
Showing 26–50 of 68 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8450849 | Robust FBEOL and UBM structure of C4 interconnects | Minhua Lu, Eric D. Pefecto, Sudipta K. Ray | 2013-05-28 |
| 8338286 | Dimensionally decoupled ball limiting metalurgy | Eric David Perfecto, Harry D. Cox, Timothy H. Daubenspeck, Brian R. Sundlof | 2012-12-25 |
| 8298929 | Offset solder vias, methods of manufacturing and design structures | Timothy H. Daubenspeck, Gary LaFontant, Ekta Misra, George J. Scott, Krystyna W. Semkow +3 more | 2012-10-30 |
| 8258410 | Construction of reliable stacked via in electronic substrates—vertical stiffness control method | Karan Kacker, Douglas O. Powell, David J. Russell, Sri M. Sri-Jayantha | 2012-09-04 |
| 8242593 | Clustered stacked vias for reliable electronic substrates | Karan Kacker, Douglas O. Powell, David J. Russell, Sri M. Sri-Jayantha | 2012-08-14 |
| 8227918 | Robust FBEOL and UBM structure of C4 interconnects | Minhua Lu, Eric D. Pefecto, Sudipta K. Ray | 2012-07-24 |
| 8198133 | Structures and methods to improve lead-free C4 interconnect reliability | Timothy H. Daubenspeck, Paul F. Fortier, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter +1 more | 2012-06-12 |
| 8188597 | Fixture to constrain laminate and method of assembly | Thomas E. Lombardi, Donald A. Merte, Gregg B. Monjeau, Son K. Tran | 2012-05-29 |
| 8054630 | Electronic components on trenched substrates and method of forming same | Vijayeshwar D. Khanna, Jennifer V. Muney, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit | 2011-11-08 |
| 8037594 | Method of forming a flip-chip package | Jeffrey T. Coffin, Michael A. Gaynes, Kamal K. Sikka, Hilton T. Toy, Jamil A. Wakil | 2011-10-18 |
| 7875502 | Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners | Peter J. Brofman, Jon A. Casey, Ian D. Melville, Wolfgang Sauter, Thomas A. Wassick | 2011-01-25 |
| 7868459 | Semiconductor package having non-aligned active vias | Jean Audet, Luc Guerin, David J. Russell | 2011-01-11 |
| 7859122 | Final via structures for bond pad-solder ball interconnections | Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter | 2010-12-28 |
| 7855430 | Electronic components on trenched substrates and method of forming same | Vijayeshwar D. Khanna, Jennifer V. Muncy, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit | 2010-12-21 |
| 7851911 | Semiconductor chip used in flip chip process | Charles F. Carey, Bernt Julius Hansen, Ashwani K. Malhotra, Wolfgang Sauter | 2010-12-14 |
| 7819027 | Method and structure for a pull test for controlled collapse chip connections and ball limiting metallurgy | Virendra R. Jadhav, Vijayeshwar D. Khanna, David C. Long | 2010-10-26 |
| 7812438 | Via offsetting to reduce stress under the first level interconnect (FLI) in microelectronics packaging | Virendra R. Jadhav, Kamal K. Sikka, Xiaojin Wei, Jiantao Zheng | 2010-10-12 |
| 7795724 | Sandwiched organic LGA structure | William L. Brodsky, James A. Busby, Bruce J. Chamberlin, Mitchell G. Ferrill, Robin A. Susko | 2010-09-14 |
| 7777301 | Electronic components on trenched substrates and method of forming same | Vijayeshwar D. Khanna, Jennifer V. Muncy, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit | 2010-08-17 |
| 7732894 | Electronic components on trenched substrates and method of forming same | Vijayeshwar D. Khanna, Jennifer V. Muney, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit | 2010-06-08 |
| 7732932 | Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners | Peter J. Brofman, Jon A. Casey, Ian D. Melville, Wolfgang Sauter, Thomas A. Wassick | 2010-06-08 |
| 7678673 | Strengthening of a structure by infiltration | Elbert E. Huang, William Francis Landers, Michael Lane, Eric G. Liniger, Xiao Hu Liu +1 more | 2010-03-16 |
| 7674637 | Monitoring cool-down stress in a flip chip process using monitor solder bump structures | Charles F. Carey, Bernt Julius Hansen, Ashwani K. Malhotra, Wolfgang Sauter | 2010-03-09 |
| 7545050 | Design structure for final via designs for chip stress reduction | Timothy H. Daubenspeck, Wolfgang Sauter, Jeffrey P. Gambino | 2009-06-09 |
| 7489512 | Optimized thermally conductive plate and attachment method for enhanced thermal performance and reliability of flip chip organic packages | Jeffrey T. Coffin, Michael A. Gaynes, Kamal K. Sikka, Hilton T. Toy, Jamil A. Wakil | 2009-02-10 |