Issued Patents All Time
Showing 476–500 of 694 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9462692 | Test structure and method of testing electrical characteristics of through vias | Shang-Yun Hou, Wei-Cheng Wu, Hsien-Pin Hu, Jung Cheng Ko, Chen-Hua Yu +1 more | 2016-10-04 |
| 9461025 | Electric magnetic shielding structure in packages | Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Jie Chen | 2016-10-04 |
| 9455183 | Semiconductor device and bump formation process | Yi-Li Hsiao, Chen-Hua Yu, Chih-Hang Tung, Cheng-Chang Wei | 2016-09-27 |
| 9449947 | Semiconductor package for thermal dissipation | Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Cheng-Chieh Hsieh, Ming-Yen Chiu | 2016-09-20 |
| 9443806 | Chip packages and methods of manufacturing the same | Cheng-Chieh Hsieh, Tsung-Shu Lin, Chen-Hua Yu | 2016-09-13 |
| 9418876 | Method of three dimensional integrated circuit assembly | Jing-Cheng Lin, Weng-Jin Wu, Shih-Ting Lin, Cheng-Lin Huang, Szu-Wei Lu +1 more | 2016-08-16 |
| 9412678 | Structure and method for 3D IC package | Shang-Yun Hou, Der-Chyang Yeh, Chen-Hua Yu | 2016-08-09 |
| 9406650 | Methods of packaging semiconductor devices and packaged semiconductor devices | Wen-Chih Chiou, Tu-Hao Yu, Hung-Jung Tu, Yu-Liang Lin, Shih-Hui Wang | 2016-08-02 |
| 9385095 | 3D semiconductor package interposer with die cavity | Shang-Yun Hou, Kim Hong Chen, Wensen Hung, Szu-Po Huang | 2016-07-05 |
| 9379036 | 3DIC packages with heat dissipation structures | Wensen Hung, Szu-Po Huang, Kim Hong Chen | 2016-06-28 |
| 9372206 | Testing of semiconductor chips with microbumps | Wei-Cheng Wu, Hsien-Pin Hu, Shang-Yun Hou, Chen-Hua Yu, Chao-Hsiang Yang | 2016-06-21 |
| 9372951 | Semiconductor device design methods and conductive bump pattern enhancement methods | Tzu-Yu Wang, Wei-Cheng Wu, Kuo-Ching Hsu, Shang-Yun Hou | 2016-06-21 |
| 9349701 | Self-aligning conductive bump structure and method of fabrication | Cheng-Lin Huang, I-Ting Chen, Ying-Ching Shih, Po-Hao Tsai, Szu-Wei Lu +2 more | 2016-05-24 |
| 9349655 | Method for mechanical stress enhancement in semiconductor devices | Carlos H. Diaz, Yi-Ming Sheu, Anson Wang, Kong-Beng Thei, Sheng-Chen Chung +3 more | 2016-05-24 |
| 9337118 | Stress buffer structures in a mounting structure of a semiconductor device | Tzu-Yu Wang, Tzu-Wei Chiu | 2016-05-10 |
| 9337123 | Thermal structure for integrated circuit package | Cheng-Chieh Hsieh, Way Lee Cheng, Shang-Yun Hou | 2016-05-10 |
| 9312149 | Method for forming chip-on-wafer assembly | Jing-Cheng Lin, Cheng-Lin Huang, Szu-Wei Lu, Jui-Pin Hung, Chen-Hua Yu | 2016-04-12 |
| 9305808 | Methods and apparatus of packaging with interposers | Chung-Yu Lu, Hsien-Pin Hu, Hsiao-Tsung Yen, Tzuan-Horng Liu, Shih-Wen Huang +1 more | 2016-04-05 |
| 9305769 | Thin wafer handling method | Chen-Hua Yu, Wen-Chih Chiou, Hung-Jung Tu | 2016-04-05 |
| 9299676 | Through silicon via structure | Chen-Hua Yu, Wen-Chih Chiou, Fang Wen Tsai, Chen-Yu Tsai | 2016-03-29 |
| 9299649 | 3D packages and methods for forming the same | Tzu-Wei Chiu, Cheng-Hsien Hsieh, Hsien-Pin Hu, Kuo-Ching Hsu, Shang-Yun Hou | 2016-03-29 |
| 9293369 | Three-dimensional integrated circuit (3DIC) | Chih-Wei Wu, Szu-Wei Lu, Jing-Cheng Lin, Chen-Hua Yu | 2016-03-22 |
| 9281297 | Solution for reducing poor contact in info packages | Jing-Cheng Lin, Chen-Hua Yu, Szu-Wei Lu, Shih-Ting Lin | 2016-03-08 |
| 9275948 | Integrated circuit having stress tuning layer | Clinton Chao, Szu-Wei Lu | 2016-03-01 |
| 9269694 | Packages with thermal management features for reduced thermal crosstalk and methods of forming same | Kim Hong Chen, Wensen Hung, Szu-Po Huang | 2016-02-23 |