Issued Patents All Time
Showing 451–475 of 694 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9633954 | Methods of manufacturing an integrated circuit having stress tuning layer | Clinton Chao, Szu-Wei Lu | 2017-04-25 |
| 9633929 | TSV formation | Ku-Feng Yang, Wen-Chih Chiou | 2017-04-25 |
| 9633900 | Method for through silicon via structure | Chen-Hua Yu, Wen-Chih Chiou, Fang Wen Tsai, Chen-Yu Tsai | 2017-04-25 |
| 9627223 | Methods and apparatus of packaging with interposers | Chung-Yu Lu, Hsien-Pin Hu, Hsiao-Tsung Yen, Tzuan-Horng Liu, Shih-Wen Huang +1 more | 2017-04-18 |
| 9618572 | Testing of semiconductor chips with microbumps | Wei-Cheng Wu, Hsien-Pin Hu, Shang-Yun Hou, Chen-Hua Yu, Chao-Hsiang Yang | 2017-04-11 |
| 9601446 | Method of fabricating a bond pad structure | Hsien-Wei Chen, Hao-Yi Tsai, Yu-Wen Liu | 2017-03-21 |
| 9601443 | Test structure for seal ring quality monitor | Hao-Yi Tsai, Shih-Hsun Hsu, Shih-Cheng Chang, Shang-Yun Hou, Hsien-Wei Chen +3 more | 2017-03-21 |
| 9595510 | Structure and formation method for chip package | Jui-Pin Hung, Cheng-Lin Huang, Hsien-Wen Liu | 2017-03-14 |
| 9595506 | Packages with thermal management features for reduced thermal crosstalk and methods of forming same | Kim Hong Chen, Wensen Hung, Szu-Po Huang | 2017-03-14 |
| 9589857 | Interposer test structures and methods | Tzuan-Horng Liu, Chen-Hua Yu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu +1 more | 2017-03-07 |
| 9583415 | Packages with thermal interface material on the sidewalls of stacked dies | Chen-Hua Yu, Wensen Hung, Szu-Po Huang, An-Jhih Su, Hsiang-Fan Lee +2 more | 2017-02-28 |
| 9581638 | Chip-on-wafer process control monitoring for chip-on-wafer-on-substrate packages | Wei-Cheng Wu, Li-Han Hsu, Sao-Ling Chiu, Shang-Yun Hou, Chen-Hua Lin | 2017-02-28 |
| 9576926 | Pad structure design in fan-out package | Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen | 2017-02-21 |
| 9576938 | 3DIC packages with heat dissipation structures | Wensen Hung, Szu-Po Huang, Kim Hong Chen | 2017-02-21 |
| 9570366 | Passivation layer for packaged chip | Wei-Cheng Wu, Shang-Yun Hou, Chen-Hua Yu, Tzuan-Horng Liu, Tzu-Wei Chiu +1 more | 2017-02-14 |
| 9570324 | Method of manufacturing package system | Wei-Cheng Wu, Shang-Yun Hou, Chen-Hua Yu | 2017-02-14 |
| 9553000 | Interconnect structure for wafer level package | Chen-Hua Yu, Jing-Cheng Lin, Nai-Wei Liu, Jui-Pin Hung | 2017-01-24 |
| 9553053 | Bump structure for yield improvement | Tzu-Wei Chiu, Tzu-Yu Wang, Shang-Yun Hou, Hsien-Wei Chen, Hung-An Teng +1 more | 2017-01-24 |
| 9530730 | Configurable routing for packaging applications | Chung-Yu Lu, Hsien-Pin Hu, Shang-Yun Hou, Tzuan-Horng Liu, Shih-Wen Huang +1 more | 2016-12-27 |
| 9524942 | Chip-on-substrate packaging on carrier | Chen-Hua Yu, Tzu-Shiun Sheu, Shih-Peng Tai, An-Jhih Su, Chi-Hsi Wu | 2016-12-20 |
| 9520372 | Wafer level package (WLP) and method for forming the same | Hsien-Wen Liu | 2016-12-13 |
| 9508666 | Packaging structures and methods with a metal pillar | Chen-Hua Yu, Shang-Yun Hou, Kuo-Ching Hsu, Cheng-Chieh Hsieh, Ying-Ching Shih +3 more | 2016-11-29 |
| 9496235 | Pillar design for conductive bump | Cheng-Chieh Hsieh, Cheng-Lin Huang, Po-Hao Tsai, Shang-Yun Hou, Jing-Cheng Lin | 2016-11-15 |
| 9496249 | 3DIC package and methods of forming the same | Kim Hong Chen, Szu-Po Huang, Wensen Hung | 2016-11-15 |
| 9478480 | Alignment mark and method of formation | Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai +4 more | 2016-10-25 |