Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11824027 | Semiconductor package | — | 2023-11-21 |
| 11164825 | CoWos interposer with selectable/programmable capacitance arrays | Liang-Chen Lin | 2021-11-02 |
| 10833034 | Semiconductor package | — | 2020-11-10 |
| 10014252 | Integrated circuit with multi-level arrangement of e-fuse protected decoupling capacitors | Liang-Chen Lin, Fu-Tsai Hou, Tung-Chin Yeh, Shih-Kai Lin, Gia-Her Lu +2 more | 2018-07-03 |
| 9601443 | Test structure for seal ring quality monitor | Hao-Yi Tsai, Shih-Hsun Hsu, Shang-Yun Hou, Hsien-Wei Chen, Chia-Lun Tsai +3 more | 2017-03-21 |
| 9385079 | Methods for forming stacked capacitors with fuse protection | Liang-Chen Lin, Fu-Tsai Hou, Tung-Chin Yeh, Shih-Kai Lin, Gia-Her Lu +2 more | 2016-07-05 |
| 9269485 | Method of creating spiral inductor having high Q value | Hui Yu Lee | 2016-02-23 |
| 9105696 | Method of coating surface of substrate hole with layer of reduced graphene oxide | Wei-Ping Dow | 2015-08-11 |
| 8670637 | Optical clock signal distribution using through-silicon vias | Jin-Lien Lin, Kuo-Ching Hsu, Kai-Ming Ching, Jiun Yi Wu, Yen-Huei Chen | 2014-03-11 |
| 8026567 | Thermoelectric cooler for semiconductor devices with TSV | Hsin-Yu Pan | 2011-09-27 |
| 8005326 | Optical clock signal distribution using through-silicon vias | Jin-Lien Lin, Kuo-Ching Hsu, Kai-Ming Ching, Jiun Yi Wu, Yen-Huei Chen | 2011-08-23 |
| 7615487 | Power delivery package having through wafer vias | — | 2009-11-10 |
| 7539094 | Multi-bit stream of multimedia data processing | Chi-Hsien Shih | 2009-05-26 |
| 7257784 | Method for integrally checking chip and package substrate layouts for errors | Chia-Lin Cheng, EJ Wu, Kuo-Yin Chen | 2007-08-14 |
| 7216324 | Method for designing chip package by re-using existing mask designs | — | 2007-05-08 |