Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12283589 | Semiconductor device including cumulative sealing structures | — | 2025-04-22 |
| 11742276 | Semiconductor package and manufacturing process thereof | Li-Huan Chu, Hsu-Hsien Chen, Tsung-Yang Hsieh, Hsin-Hsien Lee, Kuen-Hong Tsai | 2023-08-29 |
| 11676958 | Semiconductor device including cumulative sealing structures and method and system for making of same | — | 2023-06-13 |
| 11315860 | Semiconductor package and manufacturing process thereof | Li-Huan Chu, Hsu-Hsien Chen, Tsung-Yang Hsieh, Hsin-Hsien Lee, Kuen-Hong Tsai | 2022-04-26 |
| 11226363 | Reliability testing method and apparatus | Shiang-Ruei Su, Chia-Wei Tu | 2022-01-18 |
| 11164825 | CoWos interposer with selectable/programmable capacitance arrays | Shih-Cheng Chang | 2021-11-02 |
| 10847492 | Semiconductor structure and manufacturing method for the same | Jyun-Lin Wu, Shiang-Ruei Su | 2020-11-24 |
| 10495687 | Reliability testing method | Shiang-Ruei Su, Chia-Wei Tu | 2019-12-03 |
| 10014252 | Integrated circuit with multi-level arrangement of e-fuse protected decoupling capacitors | Shih-Cheng Chang, Fu-Tsai Hou, Tung-Chin Yeh, Shih-Kai Lin, Gia-Her Lu +2 more | 2018-07-03 |
| 9711474 | Semiconductor package structure with polymeric layer and manufacturing method thereof | Gia-Her Lu, Tung-Chin Yeh, Jyun-Lin Wu, Tung-Jiun Wu | 2017-07-18 |
| 9508617 | Test chip, test board and reliability testing method | Shiang-Ruei Su, Chia-Wei Tu | 2016-11-29 |
| 9385079 | Methods for forming stacked capacitors with fuse protection | Shih-Cheng Chang, Fu-Tsai Hou, Tung-Chin Yeh, Shih-Kai Lin, Gia-Her Lu +2 more | 2016-07-05 |
| 8952945 | Display and gate driver thereof | Kuan-Chun Huang, Chen Lei, Pi-Chun Yeh | 2015-02-10 |
| 8441127 | Bump-on-trace structures with wide and narrow portions | Fu-Tsai Hou | 2013-05-14 |
| 8217520 | System-in-package packaging for minimizing bond wire contamination and yield loss | Pei-Haw Tsao, Bill Kiang, Pao-Kang Niu, I-Tai Liu | 2012-07-10 |
| 7939824 | Test structure | Ta-Chih Peng, Yu-Ting Lin, Ko-Yi Lee | 2011-05-10 |
| 7843058 | Flip chip packages with spacers separating heat sinks and substrates | Pei-Haw Tsao, Pao-Kang Niu | 2010-11-30 |
| 7719122 | System-in-package packaging for minimizing bond wire contamination and yield loss | Pei-Haw Tsao, Bill Kiang, Pao-Kang Niu, I-Tai Liu | 2010-05-18 |
| 7679180 | Bond pad design to minimize dielectric cracking | Pei-Haw Tsao, Pao-Kang Niu, I-Tai Liu, Bill Kiang | 2010-03-16 |
| 7659632 | Solder bump structure and method of manufacturing same | Pei-Haw Tsao, Bill Kiang, Pao-Kang Niu, I-Tai Liu | 2010-02-09 |
| 7498680 | Test structure | Ta-Chih Peng, Yu-Ting Lin, Ko-Yi Lee | 2009-03-03 |
| 7397127 | Bonding and probing pad structures | Pei-Haw Tsao | 2008-07-08 |
| 6365455 | Flash memory process using polysilicon spacers | Wen-Doe Su, Thomas Chang, Kuo-Tung Sung, Mao-Song Tseng, Shih-Chi Lai +1 more | 2002-04-02 |