KD

Kristof Darmawikarta

IN Intel: 95 patents #223 of 30,777Top 1%
SH Santa Clara Holdings: 1 patents #1 of 24Top 5%
TR Tahoe Research: 1 patents #81 of 215Top 40%
📍 Chandler, AZ: #22 of 3,331 inventorsTop 1%
🗺 Arizona: #134 of 32,909 inventorsTop 1%
Overall (All Time): #15,004 of 4,157,543Top 1%
98
Patents All Time

Issued Patents All Time

Showing 26–50 of 98 patents

Patent #TitleCo-InventorsDate
11942334 Microelectronic assemblies having conductive structures with different thicknesses Jeremy Ecton, Aleksandar Aleksov, Suddhasattwa Nad, Vahidreza Parichehreh, Veronica Strong +1 more 2024-03-26
11929212 Method to form high capacitance thin film capacitors (TFCs) as embedded passives in organic substrate packages Sameer Paital, Gang Duan, Srinivas V. Pietambaram 2024-03-12
11929330 Lithographic cavity formation to enable EMIB bump pitch scaling Hiroki Tanaka, Robert Alan May, Sameer Paital, Bai Nie, Jesse C. Jones +1 more 2024-03-12
11923312 Patternable die attach materials and processes for patterning Bai Nie, Gang Duan, Srinivas V. Pietambaram, Jesse C. Jones, Yosuke Kanaoka +10 more 2024-03-05
11908802 Multi-chip package with high density interconnects Aleksandar Aleksov, Adel A. Elsherbini, Robert Alan May, Sri Ranga Sai Boyapati 2024-02-20
11908821 Sacrificial dielectric for lithographic via formation to enable via scaling in high density interconnect packaging Sri Ranga Sai Boyapati, Hiroki Tanaka, Robert Alan May 2024-02-20
11901296 Die interconnect substrate, an electrical device and a method for forming a die interconnect substrate Robert Alan May, Sri Ranga Sai Boyapati 2024-02-13
11894324 In-package RF waveguides as high bandwidth chip-to-chip interconnects and methods for using the same Aleksandar Aleksov, Telesphor Kamgaing, Sri Ranga Sai Boyapati, Eyal Fayneh, Ofir Degani +2 more 2024-02-06
11894311 Microelectronic device with embedded die substrate on interposer Robert Alan May, Islam A. Salama, Sri Ranga Sai Boyapati, Sheng Li, Robert L. Sankman +1 more 2024-02-06
11862619 Patch accommodating embedded dies having different thicknesses Srinivas V. Pietambaram, Robert Alan May, Hiroki Tanaka, Rahul N. Manepalli, Sri Ranga Sai Boyapati 2024-01-02
11854834 Integrated circuit package supports Robert Alan May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov 2023-12-26
11837534 Substrate with variable height conductive and dielectric elements Aleksandar Aleksov, Haobo Chen, Changhua Liu, Sri Ranga Sai Boyapati, Bai Nie 2023-12-05
11804455 Substrate integrated thin film capacitors using amorphous high-k dielectrics Aleksandar Aleksov, Thomas L. Sounart, Henning Braunisch, Prithwish Chatterjee, Andrew J. Brown 2023-10-31
11798887 Inorganic-based embedded-die layers for modular semiconductive devices Srinivas V. Pietambaram, Tarek A. Ibrahim, Rahul N. Manepalli, Debendra Mallik, Robert L. Sankman 2023-10-24
11791228 Method for forming embedded grounding planes on interconnect layers Brandon C. Marin, Roy Dittler, Jeremy Ecton, Darko Grujicic 2023-10-17
11784128 Die interconnect substrate, an electrical device and a method for forming a die interconnect substrate Robert Alan May, Sri Ranga Sai Boyapati 2023-10-10
11735531 Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers Srinivas V. Pietambaram, Sri Ranga Sai Boyapati, Robert Alan May, Javier Soto Gonzalez, Kwangmo Chris Lim 2023-08-22
11728258 Electroless metal-defined thin pad first level interconnects for lithographically defined vias Aleksandar Aleksov, Veronica Strong, Arnab Sarkar 2023-08-15
11699648 Electromigration resistant and profile consistent contact arrays Srinivas V. Pietambaram, Jung Kyu Han, Ali Lehaf, Steve Cho, Thomas HEATON +3 more 2023-07-11
11652036 Via-trace structures Jeremy Ecton, Hiroki Tanaka, Oscar Ojeda, Arnab Roy, Nicholas S. Haehn 2023-05-16
11605867 Fabricating an RF filter on a semiconductor package using selective seeding Brandon C. Marin, Jeremy Ecton, Aleksandar Aleksov, Yonggang Li, Dilan Seneviratne 2023-03-14
11574874 Package architecture utilizing photoimageable dielectric (PID) for reduced bump pitch Robert Alan May, Sri Ranga Sai Boyapati, Hiroki Tanaka, Srinivas V. Pietambaram, Frank Truong +4 more 2023-02-07
11552010 Dielectric for high density substrate interconnects Robert Alan May, Andrew J. Brown, Sri Ranga Sai Boyapati 2023-01-10
11532584 Package substrate with high-density interconnect layer having pillar and via connections for fan out scaling Robert Alan May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Javier Soto Gonzalez, Kwangmo Chris Lim +1 more 2022-12-20
11521931 Microelectronic structures including bridges Jason M. Gamba, Nitin A. Deshpande, Mohit Bhatia, Omkar G. Karhade, Bai Nie +2 more 2022-12-06