JG

Javier Soto Gonzalez

IN Intel: 22 patents #1,785 of 30,777Top 6%
TR Tahoe Research: 1 patents #81 of 215Top 40%
Overall (All Time): #176,612 of 4,157,543Top 5%
23
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12218071 Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers Srinivas V. Pietambaram, Sri Ranga Sai Boyapati, Robert Alan May, Kristof Darmawikarta, Kwangmo Chris Lim 2025-02-04
12199067 Scalable embedded silicon bridge via pillars in lithographically defined vias, and methods of making same Adel A. Elsherbini, Henning Braunisch, Shawna M. Liff 2025-01-14
12068172 Sacrificial pads to prevent galvanic corrosion of FLI bumps in EMIB packages Tarek A. Ibrahim, Rahul N. Manepalli, Wei-Lun Kane Jen, Steve Cho, Jason M. Gamba 2024-08-20
12002745 High performance integrated RF passives using dual lithography process Adel A. Elsherbini, Mathew J. Manusharow, Krishna Bharath, William J. Lambert, Robert L. Sankman +6 more 2024-06-04
11881457 Semiconductor packaging with high density interconnects Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Henning Braunisch, Krishna Bharath +1 more 2024-01-23
11735531 Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers Srinivas V. Pietambaram, Sri Ranga Sai Boyapati, Robert Alan May, Kristof Darmawikarta, Kwangmo Chris Lim 2023-08-22
11532584 Package substrate with high-density interconnect layer having pillar and via connections for fan out scaling Robert Alan May, Sri Ranga Sai Boyapati, Kristof Darmawikarta, Srinivas V. Pietambaram, Kwangmo Chris Lim +1 more 2022-12-20
11227825 High performance integrated RF passives using dual lithography process Adel A. Elsherbini, Mathew J. Manusharow, Krishna Bharath, William J. Lambert, Robert L. Sankman +6 more 2022-01-18
11101222 Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers Srinivas V. Pietambaram, Sri Ranga Sai Boyapati, Robert Alan May, Kristof Darmawikarta, Kwangmo Chris Lim 2021-08-24
11004824 Scalable embedded silicon bridge via pillars in lithographically defined vias, and methods of making same Adel A. Elsherbini, Henning Braunisch, Shawna M. Liff 2021-05-11
10978399 Die interconnect substrate, an electrical device, and a method for forming a die interconnect substrate Kristof Darmawikarta, Robert Alan May, Sri Ranga Sai Boyapati, Wei-Lun Kane Jen 2021-04-13
10971453 Semiconductor packaging with high density interconnects Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Henning Braunisch, Krishna Bharath +1 more 2021-04-06
10971416 Package power delivery using plane and shaped vias Krishna Bharath, Mathew J. Manusharow, Adel A. Elsherbini, Mihir K. Roy, Aleksandar Aleksov +4 more 2021-04-06
10872872 Package substrate with high-density interconnect layer having pillar and via connections for fan out scaling Robert Alan May, Sri Ranga Sai Boyapati, Kristof Darmawikarta, Srinivas V. Pietambaram, Kwangmo Chris Lim +1 more 2020-12-22
10798817 Method for making a flexible wearable circuit Aleksandar Aleksov, Meizi Jiao, Shruti R. Jaywant, Oscar Ojeda, Sashi S. Kandanur +4 more 2020-10-06
10410939 Package power delivery using plane and shaped vias Krishna Bharath, Mathew J. Manusharow, Adel A. Elsherbini, Mihir K. Roy, Aleksandar Aleksov +4 more 2019-09-10
10327330 Stretchable electronic assembly Aleksandar Aleksov, Adel A. Elsherbini, Dilan Seneviratne, Shruti R. Jaywant, Sashi S. Kandanur +5 more 2019-06-18
10204855 Bendable and stretchable electronic devices and methods Alejandro X. Levander, Tatyana N. Andryushchenko, David Staines, Mauro J. Kobrinsky, Aleksandar Aleksov +3 more 2019-02-12
9832860 Panel level fabrication of package substrates with integrated stiffeners Robert Starkston, John S. Guzek, Patrick Nardi, Keith Jones 2017-11-28
9780054 Semiconductor package with embedded die and its methods of fabrication John S. Guzek, Nicholas R. Watts, Ravi Kiran Nalla 2017-10-03
9691727 Pad-less interconnect for electrical coreless substrate Charavana K. Gurumurthy, Robert M. Nickerson, Debendra Mallik 2017-06-27
9505607 Methods of forming sensor integrated packages and structures formed thereby Kyu Oh Lee, Zheng Zhou, Islam A. Salama, Feras Eid, Sasha N. Oster +1 more 2016-11-29
9165914 Forming die backside coating structures with coreless packages Rahul N. Manepalli, Mohit Mamodia, David Xu, Edward R. Prack 2015-10-20