Issued Patents 2016
Showing 1–25 of 114 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9530715 | Thermally enhanced structure for multi-chip device | Chih-Hang Tung, Tung-Liang Shao | 2016-12-27 |
| 9530759 | 3D package with through substrate vias | Mirng-Ji Lii, Hung-Yi Kuo, Hao-Yi Tsai, Chao-Wen Shih, Tsung-Yuan Yu +1 more | 2016-12-27 |
| 9530757 | Single mask package apparatus | Mirng-Ji Lii, Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo | 2016-12-27 |
| 9530762 | Semiconductor package, semiconductor device and method of forming the same | Chung-Shi Liu, Chih-Fan Huang, Tsai-Tsung Tsai, Wei-Hung Lin, Ming-Da Cheng | 2016-12-27 |
| 9524942 | Chip-on-substrate packaging on carrier | Tzu-Shiun Sheu, Shin-Puu Jeng, Shih-Peng Tai, An-Jhih Su, Chi-Hsi Wu | 2016-12-20 |
| 9524956 | Integrated fan-out structure and method | Hao-Jan Pei, Hui-Min Huang, Hsiu-Jen Lin, Ming-Da Cheng, Chung-Shi Liu | 2016-12-20 |
| 9524959 | System on integrated chips and methods of forming same | Sung-Feng Yeh, Ming-Fa Chen | 2016-12-20 |
| 9520340 | Semiconductor die connection system and method | Ming-Fa Chen, Sen-Bor Jan | 2016-12-13 |
| 9521795 | Two-step direct bonding processes and tools for performing the same | Yi-Li Hsiao, Da-Yuan Shih, Chih-Hang Tung | 2016-12-13 |
| 9515036 | Methods and apparatus for solder connections | Hao-Yi Tsai, Chien-Hsiun Lee, Chung-Shi Liu, Hsien-Wei Chen | 2016-12-06 |
| 9508666 | Packaging structures and methods with a metal pillar | Shin-Puu Jeng, Shang-Yun Hou, Kuo-Ching Hsu, Cheng-Chieh Hsieh, Ying-Ching Shih +3 more | 2016-11-29 |
| 9508703 | Stacked dies with wire bonds and method | Ming-Fa Chen, Sung-Feng Yeh, Meng-Tse Chen, Hui-Min Huang, Hsiu-Jen Lin +2 more | 2016-11-29 |
| 9508664 | Semiconductor device structure comprising a plurality of metal oxide fibers and method for forming the same | Jing-Cheng Lin, Szu-Wei Lu, Yen-Yao Chi | 2016-11-29 |
| 9502386 | Fan-out package structure and methods for forming the same | Der-Chyang Yeh | 2016-11-22 |
| 9502343 | Dummy metal with zigzagged edges | Cheng-Hsien Hsieh, Hsien-Wei Chen, Chi-Hsi Wu, Der-Chyang Yeh, Li-Han Hsu +1 more | 2016-11-22 |
| 9498851 | Methods for forming apparatus for stud bump formation | Yeong-Jyh Lin, Hsin-Hung Liao, Chien Ling Hwang, Yi-Li Hsiao, Chung-Shi Liu +1 more | 2016-11-22 |
| 9502271 | Warpage control for flexible substrates | Shih-Ting Lin, Jing-Cheng Lin, Shang-Yun Hou, Szu-Wei Lu | 2016-11-22 |
| 9502394 | Package on-Package (PoP) structure including stud bulbs and method | Mirng-Ji Lii, Chung-Shi Liu, Ming-Da Cheng | 2016-11-22 |
| 9496196 | Packages and methods of manufacture thereof | Kuo-Chung Yee | 2016-11-15 |
| 9496189 | Stacked semiconductor devices and methods of forming same | Chien-Hsun Lee, Tsung-Ding Wang, Jung Wei Cheng | 2016-11-15 |
| 9484285 | Interconnect structures for wafer level package and methods of forming same | Meng-Tse Chen, Chih-Wei Lin, Hui-Min Huang, Ming-Da Cheng, Chung-Shi Liu | 2016-11-01 |
| 9475145 | Solder bump joint in a device including lamellar structures | Su-Chun Yang, Chung-Jung Wu, Hsiao-Yun Chen, Yi-Li Hsiao, Chih-Hang Tung +1 more | 2016-10-25 |
| 9478480 | Alignment mark and method of formation | Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai +4 more | 2016-10-25 |
| D769009 | Seat | Philippe Erhel, Adrian Goring, Dorothee Redon | 2016-10-18 |
| 9472552 | CMOS devices having dual high-mobility channels | Ding-Yuan Chen | 2016-10-18 |