Issued Patents 2016
Showing 1–25 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9530762 | Semiconductor package, semiconductor device and method of forming the same | Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Tsai-Tsung Tsai, Wei-Hung Lin | 2016-12-27 |
| 9524956 | Integrated fan-out structure and method | Hao-Jan Pei, Hui-Min Huang, Hsiu-Jen Lin, Chung-Shi Liu, Chen-Hua Yu | 2016-12-20 |
| 9508703 | Stacked dies with wire bonds and method | Chen-Hua Yu, Ming-Fa Chen, Sung-Feng Yeh, Meng-Tse Chen, Hui-Min Huang +2 more | 2016-11-29 |
| 9502394 | Package on-Package (PoP) structure including stud bulbs and method | Chen-Hua Yu, Mirng-Ji Lii, Chung-Shi Liu | 2016-11-22 |
| 9484285 | Interconnect structures for wafer level package and methods of forming same | Meng-Tse Chen, Chih-Wei Lin, Hui-Min Huang, Chung-Shi Liu, Chen-Hua Yu | 2016-11-01 |
| 9484227 | Dicing in wafer level package | Chia-Shen Cheng, An-Jhih Su, Chung-Shi Liu, Hsiu-Jen Lin, Hsien-Wei Chen +1 more | 2016-11-01 |
| 9472525 | Bump-on-trace structures with high assembly yield | Chih-Fan Huang, Chen-Shien Chen, Chung-Shi Liu, Tin-Hao Kuo, Yi-Teh Chou | 2016-10-18 |
| 9449933 | Packaging device and method of making the same | Chang-Chia Huang, Tsung-Shu Lin, Wen-Hsiung Lu, Bor-Rung Su | 2016-09-20 |
| 9449934 | Solder joint structure for ball grid array in wafer level package | Yu-Hsiang Hu, Wei-Yu Chen, Wei-Hung Lin, Chung-Shi Liu | 2016-09-20 |
| 9449908 | Semiconductor package system and method | Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Chung-Shi Liu, Chen-Hua Yu | 2016-09-20 |
| 9437564 | Interconnect structure and method of fabricating same | Wen-Hsiung Lu, Hsuan-Ting Kuo, Cheng-Ting Chen, Ai-Tee Ang, Chung-Shi Liu | 2016-09-06 |
| 9427818 | Semiconductor processing boat design with pressure sensor | Ai-Tee Ang, Hsiu-Jen Lin, Wei-Hung Lin, Chung-Shi Liu | 2016-08-30 |
| 9431360 | Semiconductor structure and manufacturing method thereof | Hsuan-Ting Kuo, Yu-Peng Tsai, Wei-Hung Lin, Chun-Lung Jao, Chao-Wen Shih +1 more | 2016-08-30 |
| 9425157 | Substrate and package structure | Wei-Hung Lin, Hsiu-Jen Lin, Yu-Min Liang, Chen-Shien Chen, Chung-Shi Liu | 2016-08-23 |
| 9425178 | RDL-first packaging process | Chih-Wei Lin, Shing-Chao Chen, Meng-Tse Chen, Chung-Shi Liu | 2016-08-23 |
| 9418978 | Method of forming package-on-package (PoP) structure having a chip package with a plurality of dies attaching to first side of an interposer with a die formed thereon | Chen-Hua Yu, Chung-Shi Liu, Mirng-Ji Lii, Chih-Wei Lin | 2016-08-16 |
| 9418971 | Package-on-package structure including a thermal isolation material and method of forming the same | Meng-Tse Chen, Kuei-Wei Huang, Tsai-Tsung Tsai, Ai-Tee Ang, Chung-Shi Liu | 2016-08-16 |
| 9418947 | Mechanisms for forming connectors with a molding compound for package on package | Yu-Feng Chen, Chun-Hung Lin, Han-Ping Pu, Kai-Chiang Wu | 2016-08-16 |
| 9412717 | Apparatus and methods for molded underfills in flip chip packaging | Meng-Tse Chen, Hsiu-Jen Lin, Chun-Cheng Lin, Wen-Hsiung Lu, Chung-Shi Liu | 2016-08-09 |
| 9412723 | Package on-package structures and methods for forming the same | Kuei-Wei Huang, Chih-Wei Lin, Hsiu-Jen Lin, Wei-Hung Lin, Chung-Shi Liu | 2016-08-09 |
| 9412689 | Semiconductor packaging structure and method | Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Cheng-Ting Chen, Wei-Hung Lin | 2016-08-09 |
| 9401337 | Molding structure for wafer level package | Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Chih-Wei Lin, Wei-Hung Lin | 2016-07-26 |
| 9397062 | Package on package bonding structure and method for forming the same | Kuei-Wei Huang, Wei-Yu Chen, Meng-Tse Chen, Wei-Hung Lin, Chung-Shi Liu | 2016-07-19 |
| 9385040 | Method of manufacturing a semiconductor device | Tsai-Tsung Tsai, Wen-Hsiung Lu, Yu-Peng Tsai, Wei-Hung Lin, Chung-Shi Liu | 2016-07-05 |
| 9373603 | Reflow process and tool | Ai-Tee Ang, Hsiu-Jen Lin, Cheng-Ting Chen, Chung-Shi Liu | 2016-06-21 |