Issued Patents 2016
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9524959 | System on integrated chips and methods of forming same | Sung-Feng Yeh, Chen-Hua Yu | 2016-12-20 |
| 9520340 | Semiconductor die connection system and method | Chen-Hua Yu, Sen-Bor Jan | 2016-12-13 |
| 9508703 | Stacked dies with wire bonds and method | Chen-Hua Yu, Sung-Feng Yeh, Meng-Tse Chen, Hui-Min Huang, Hsiu-Jen Lin +2 more | 2016-11-29 |
| 9449837 | 3D chip-on-wafer-on-substrate structure with via last process | Chen-Hua Yu, Wen-Ching Tsai | 2016-09-20 |
| 9449875 | Wafer backside interconnect structure connected to TSVs | Wen-Chih Chiou, Shau-Lin Shue | 2016-09-20 |
| 9373673 | 3-D inductor and transformer | Hsiao-Tsung Yen, Chin-Wei Kuo, Hsien-Pin Hu, Sally Liu, Jhe-Ching Lu | 2016-06-21 |
| 9355935 | Connecting through vias to devices | Yu-Young Wang, Sen-Bor Jan | 2016-05-31 |
| 9331021 | Chip-on-wafer package and method of forming same | Chen-Hua Yu, Sung-Feng Yeh | 2016-05-03 |
| 9236311 | Controlling the device performance by forming a stressed backside dielectric layer | I-Ching Lin | 2016-01-12 |