Issued Patents 2016
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9520379 | Method of forming bump structure having a side recess and semiconductor structure including the same | Chih-Horng Chang, Chen-Shien Chen, Yen-Liang Lin | 2016-12-13 |
| 9508637 | Protrusion bump pads for bond-on-trace processing | Chen-Shien Chen, Yu-Feng Chen, Yu-Wei Lin, Yu-Min Liang, Chun-Hung Lin | 2016-11-29 |
| 9508668 | Conductive contacts having varying widths and method of manufacturing same | Yen-Liang Lin, Yu-Jen Tseng, Chang-Chia Huang, Chen-Shien Chen | 2016-11-29 |
| 9496233 | Interconnection structure and method of forming same | Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Chen-Shien Chen | 2016-11-15 |
| 9484317 | Scheme for connector site spacing and resulting structures | Yu-Feng Chen, Yen-Liang Lin, Sheng-Yu Wu, Chen-Shien Chen | 2016-11-01 |
| 9472525 | Bump-on-trace structures with high assembly yield | Chih-Fan Huang, Chen-Shien Chen, Chung-Shi Liu, Ming-Da Cheng, Yi-Teh Chou | 2016-10-18 |
| 9449941 | Connecting function chips to a package to form package-on-package | Pei-Chun Tsai, Sheng-Yu Wu, Ching-Wen Hsiao, Chen-Shien Chen, Chung-Shi Liu +2 more | 2016-09-20 |
| 9431351 | Semiconductor package and manufacturing method of the same | Guan-Yu Chen, Yu-Wei Lin, Chen-Shien Chen | 2016-08-30 |
| 9425180 | Treating copper surfaces for packaging | Chih-Horng Chang | 2016-08-23 |
| 9425117 | Substrate design with balanced metal and solder resist density | Yu-Wei Lin, Guan-Yu Chen, Yu-Min Liang, Chen-Shien Chen | 2016-08-23 |
| 9425136 | Conical-shaped or tier-shaped pillar connections | Chen-Shien Chen, Mirng-Ji Lii, Chen-Hua Yu, Sheng-Yu Wu, Yao-Chun Chuang | 2016-08-23 |
| 9406634 | Package structure and method of forming the same | Yuh Chern Shieh, Han-Ping Pu, Yu-Feng Chen | 2016-08-02 |
| 9318458 | Bump structure having a side recess and semiconductor structure including the same | Chih-Horng Chang, Chen-Shien Chen, Yen-Liang Lin | 2016-04-19 |
| 9293449 | Methods and apparatus for package on package devices with reversed stud bump through via interconnections | Shou-Cheng Hu, Chen-Shien Chen, Chih-Hua Chen, Ching-Wen Hsiao | 2016-03-22 |
| 9287234 | Dummy flip chip bumps for reducing stress | Sheng-Yu Wu, Chita Chuang, Chen-Shien Chen | 2016-03-15 |
| 9269688 | Bump-on-trace design for enlarge bump-to-trace distance | Sheng-Yu Wu, Chen-Shien Chen | 2016-02-23 |
| 9257385 | Landing areas of bonding structures | Chih-Horng Chang, Chen-Shien Chen | 2016-02-09 |