Issued Patents 2016
Showing 1–25 of 68 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9530762 | Semiconductor package, semiconductor device and method of forming the same | Chen-Hua Yu, Chih-Fan Huang, Tsai-Tsung Tsai, Wei-Hung Lin, Ming-Da Cheng | 2016-12-27 |
| 9524945 | Cu pillar bump with L-shaped non-metal sidewall protection structure | Chien Ling Hwang, Yi-Wen Wu | 2016-12-20 |
| 9524956 | Integrated fan-out structure and method | Hao-Jan Pei, Hui-Min Huang, Hsiu-Jen Lin, Ming-Da Cheng, Chen-Hua Yu | 2016-12-20 |
| 9515036 | Methods and apparatus for solder connections | Chen-Hua Yu, Hao-Yi Tsai, Chien-Hsiun Lee, Hsien-Wei Chen | 2016-12-06 |
| 9508703 | Stacked dies with wire bonds and method | Chen-Hua Yu, Ming-Fa Chen, Sung-Feng Yeh, Meng-Tse Chen, Hui-Min Huang +2 more | 2016-11-29 |
| 9498851 | Methods for forming apparatus for stud bump formation | Yeong-Jyh Lin, Hsin-Hung Liao, Chien Ling Hwang, Yi-Li Hsiao, Mirng-Ji Lii +1 more | 2016-11-22 |
| 9502394 | Package on-Package (PoP) structure including stud bulbs and method | Chen-Hua Yu, Mirng-Ji Lii, Ming-Da Cheng | 2016-11-22 |
| 9484285 | Interconnect structures for wafer level package and methods of forming same | Meng-Tse Chen, Chih-Wei Lin, Hui-Min Huang, Ming-Da Cheng, Chen-Hua Yu | 2016-11-01 |
| 9484227 | Dicing in wafer level package | Chia-Shen Cheng, An-Jhih Su, Hsiu-Jen Lin, Hsien-Wei Chen, Ming-Da Cheng +1 more | 2016-11-01 |
| 9484226 | Methods for controlling warpage in packaging | Chien Ling Hwang, Bor-Ping Jang, Hsin-Hung Liao, Yeong-Jyh Lin, Hsiao-Chung Liang | 2016-11-01 |
| 9472525 | Bump-on-trace structures with high assembly yield | Chih-Fan Huang, Chen-Shien Chen, Ming-Da Cheng, Tin-Hao Kuo, Yi-Teh Chou | 2016-10-18 |
| 9460939 | Package-on-package structures and methods of manufacture thereof | Pei-Hsuan Lee, Chien Ling Hwang, Chen-Hua Yu | 2016-10-04 |
| 9449941 | Connecting function chips to a package to form package-on-package | Pei-Chun Tsai, Sheng-Yu Wu, Ching-Wen Hsiao, Tin-Hao Kuo, Chen-Shien Chen +2 more | 2016-09-20 |
| 9449931 | Pillar bumps and process for making same | Cheng-Chung Lin, Meng-Wei Chou, Kuo-Cheng Lin, Wen-Hsiung Lu, Chien Ling Hwang +2 more | 2016-09-20 |
| 9449908 | Semiconductor package system and method | Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Ming-Da Cheng, Chen-Hua Yu | 2016-09-20 |
| 9449934 | Solder joint structure for ball grid array in wafer level package | Yu-Hsiang Hu, Wei-Yu Chen, Wei-Hung Lin, Ming-Da Cheng | 2016-09-20 |
| 9437564 | Interconnect structure and method of fabricating same | Wen-Hsiung Lu, Hsuan-Ting Kuo, Cheng-Ting Chen, Ai-Tee Ang, Ming-Da Cheng | 2016-09-06 |
| 9430605 | Adjusting sizes of connectors of package components | Chih-Wei Lai, Ming-Che Ho, Tzong-Hann Yang, Chien Rhone Wang, Chia-Tung Chang +1 more | 2016-08-30 |
| 9427818 | Semiconductor processing boat design with pressure sensor | Ai-Tee Ang, Hsiu-Jen Lin, Wei-Hung Lin, Ming-Da Cheng | 2016-08-30 |
| 9431342 | Staggered via redistribution layer (RDL) for a package and a method for forming the same | Chen-Hua Yu, Hung-Jui Kuo | 2016-08-30 |
| 9431360 | Semiconductor structure and manufacturing method thereof | Hsuan-Ting Kuo, Yu-Peng Tsai, Wei-Hung Lin, Chun-Lung Jao, Chao-Wen Shih +1 more | 2016-08-30 |
| 9425157 | Substrate and package structure | Wei-Hung Lin, Hsiu-Jen Lin, Ming-Da Cheng, Yu-Min Liang, Chen-Shien Chen | 2016-08-23 |
| 9425178 | RDL-first packaging process | Chih-Wei Lin, Shing-Chao Chen, Meng-Tse Chen, Ming-Da Cheng | 2016-08-23 |
| 9425179 | Chip packages and methods of manufacture thereof | Chien Ling Hwang, Pei-Hsuan Lee, Ying-Jui Huang, Yeong-Jyh Lin | 2016-08-23 |
| 9418978 | Method of forming package-on-package (PoP) structure having a chip package with a plurality of dies attaching to first side of an interposer with a die formed thereon | Chen-Hua Yu, Mirng-Ji Lii, Ming-Da Cheng, Chih-Wei Lin | 2016-08-16 |