Issued Patents 2016
Showing 26–50 of 114 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9461025 | Electric magnetic shielding structure in packages | Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen, Jie Chen | 2016-10-04 |
| 9462692 | Test structure and method of testing electrical characteristics of through vias | Shang-Yun Hou, Wei-Cheng Wu, Hsien-Pin Hu, Jung Cheng Ko, Shin-Puu Jeng +1 more | 2016-10-04 |
| 9460939 | Package-on-package structures and methods of manufacture thereof | Pei-Hsuan Lee, Chien Ling Hwang, Chung-Shi Liu | 2016-10-04 |
| 9460988 | Interconnect structures | Hai-Ching Chen, Tien-I Bao | 2016-10-04 |
| 9455183 | Semiconductor device and bump formation process | Yi-Li Hsiao, Shin-Puu Jeng, Chih-Hang Tung, Cheng-Chang Wei | 2016-09-27 |
| 9455236 | Integrated circuit packages and methods of forming same | Chien-Hsun Lee, Tsung-Ding Wang, Jung Wei Cheng | 2016-09-27 |
| 9449947 | Semiconductor package for thermal dissipation | Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen, Cheng-Chieh Hsieh, Ming-Yen Chiu | 2016-09-20 |
| 9449837 | 3D chip-on-wafer-on-substrate structure with via last process | Ming-Fa Chen, Wen-Ching Tsai | 2016-09-20 |
| 9449908 | Semiconductor package system and method | Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu | 2016-09-20 |
| 9443783 | 3DIC stacking device and method of manufacture | Jing-Cheng Lin | 2016-09-13 |
| 9443806 | Chip packages and methods of manufacturing the same | Shin-Puu Jeng, Cheng-Chieh Hsieh, Tsung-Shu Lin | 2016-09-13 |
| 9443812 | Semiconductor device with post-passivation interconnect structure and method of forming the same | Hsien-Wei Chen, Tsung-Yuan Yu, Hao-Yi Tsai, Mirng-Ji Lii | 2016-09-13 |
| 9443814 | Bump structures for multi-chip packaging | Jing-Cheng Lin | 2016-09-13 |
| 9431369 | Antenna apparatus and method | Lai Wei Chih, Monsen Liu, En-Hsiang Yeh, Chuei-Tang Wang | 2016-08-30 |
| 9431342 | Staggered via redistribution layer (RDL) for a package and a method for forming the same | Chung-Shi Liu, Hung-Jui Kuo | 2016-08-30 |
| 9425128 | 3-D package having plurality of substrates | Chin-Chuan Chang, Jing-Cheng Lin | 2016-08-23 |
| 9425136 | Conical-shaped or tier-shaped pillar connections | Tin-Hao Kuo, Chen-Shien Chen, Mirng-Ji Lii, Sheng-Yu Wu, Yao-Chun Chuang | 2016-08-23 |
| 9425067 | Method for forming package systems having interposers | Yung-Chi Lin, Jing-Cheng Lin | 2016-08-23 |
| 9418961 | Apparatus and method of substrate to substrate bonding for three dimensional (3D) IC interconnects | Wen-Chih Chiou, Weng-Jin Wu | 2016-08-16 |
| 9418977 | Package-on-package semiconductor device | Der-Chyang Yeh | 2016-08-16 |
| 9418955 | Plasma treatment for semiconductor devices | Chen-Fa Lu, Chung-Shi Liu, Wei-Yu Chen, Cheng-Ting Chen | 2016-08-16 |
| 9418978 | Method of forming package-on-package (PoP) structure having a chip package with a plurality of dies attaching to first side of an interposer with a die formed thereon | Chung-Shi Liu, Mirng-Ji Lii, Ming-Da Cheng, Chih-Wei Lin | 2016-08-16 |
| 9418876 | Method of three dimensional integrated circuit assembly | Jing-Cheng Lin, Weng-Jin Wu, Shih-Ting Lin, Cheng-Lin Huang, Szu-Wei Lu +1 more | 2016-08-16 |
| 9418923 | Semiconductor component having through-silicon vias and method of manufacture | Cheng-Hung Chang, Ebin Liao, Chia-Lin Yu, Hsiang-Yi Wang, Chun Hua Chang +4 more | 2016-08-16 |
| 9418953 | Packaging through pre-formed metal pins | Chien Ling Hwang, Yeong-Jyh Lin | 2016-08-16 |