Issued Patents 2016
Showing 76–100 of 114 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9337073 | 3D shielding case and methods for forming the same | Monsen Liu, Chuei-Tang Wang, Lai Wei Chih | 2016-05-10 |
| 9331021 | Chip-on-wafer package and method of forming same | Ming-Fa Chen, Sung-Feng Yeh | 2016-05-03 |
| 9331018 | Semiconductor arrangement and formation thereof | Chung-Hao Tsai, Jeng-Shien Hsieh, Chuei-Tang Wang | 2016-05-03 |
| 9324698 | Multi-chip structure and method of forming same | Der-Chyang Yeh | 2016-04-26 |
| 9324756 | CIS chips and methods for forming the same | Wen-Chih Chiou, Jing-Cheng Lin | 2016-04-26 |
| 9324587 | Method for manufacturing semiconductor structure | Chih-Fan Huang, Chun-Hung Lin, Ming-Da Cheng, Chung-Shi Liu, Mirng-Ji Lii | 2016-04-26 |
| 9312225 | Bump structure for stacked dies | Hung-Pin Chang, Kuo-Ching Hsu, Chen-Shien Chen, Wen-Chih Chiou | 2016-04-12 |
| 9312149 | Method for forming chip-on-wafer assembly | Jing-Cheng Lin, Cheng-Lin Huang, Szu-Wei Lu, Jui-Pin Hung, Shin-Puu Jeng | 2016-04-12 |
| 9305877 | 3D package with through substrate vias | Mirng-Ji Lii, Hung-Yi Kuo, Hao-Yi Tsai, Chao-Wen Shih, Tsung-Yuan Yu +1 more | 2016-04-05 |
| 9305769 | Thin wafer handling method | Wen-Chih Chiou, Shin-Puu Jeng, Hung-Jung Tu | 2016-04-05 |
| D752352 | Seat | Philippe Erhel, Adrian Goring, Dorothee Redon | 2016-03-29 |
| 9299785 | Reducing resistance in source and drain regions of FinFETs | Yu-Rung Hsu, Chen-Nan Yeh, Cheng-Hung Chang | 2016-03-29 |
| 9299688 | Packaged semiconductor devices and methods of packaging semiconductor devices | Chung-Shi Liu, Chih-Fan Huang, Hui-Min Huang, Wei-Hung Lin, Ming-Da Cheng | 2016-03-29 |
| 9299676 | Through silicon via structure | Shin-Puu Jeng, Wen-Chih Chiou, Fang Wen Tsai, Chen-Yu Tsai | 2016-03-29 |
| 9299674 | Bump-on-trace interconnect | Chen-Shien Chen | 2016-03-29 |
| 9299612 | Stacked structures and methods of forming stacked structures | Weng-Jin Wu, Wen-Chih Chiou | 2016-03-29 |
| 9291913 | Pattern generator for a lithography system | Tien-I Bao, Chih Wei Lu, Jaw-Jung Shin, Shy-Jay Lin, Burn Jeng Lin | 2016-03-22 |
| 9293437 | Functional block stacked 3DIC and method of making same | Kuo-Chung Yee, Chih-Hang Tung | 2016-03-22 |
| 9293418 | Backside through vias in a bonded structure | Weng-Jin Wu, Ku-Feng Yang, Hung-Pin Chang, Wen-Chih Chiou | 2016-03-22 |
| 9293369 | Three-dimensional integrated circuit (3DIC) | Chih-Wei Wu, Szu-Wei Lu, Jing-Cheng Lin, Shin-Puu Jeng | 2016-03-22 |
| 9287166 | Barrier for through-silicon via | Wen-Chih Chiou, Weng-Jin Wu | 2016-03-15 |
| 9287440 | Method of manufacturing a semiconductor device including through silicon plugs | Hung-Pin Chang, Yung-Chi Lin, Chia-Lin Yu, Jui-Pin Hung, Chien Ling Hwang | 2016-03-15 |
| 9287172 | Interposer-on-glass package method | Jing-Cheng Lin | 2016-03-15 |
| 9287143 | Apparatus for package reinforcement using molding underfill | Hsien-Wei Chen, Tsung-Yuan Yu, Wen-Hsiung Lu, Ming-Da Cheng, Hao-Yi Tsai +1 more | 2016-03-15 |
| 9281297 | Solution for reducing poor contact in info packages | Jing-Cheng Lin, Szu-Wei Lu, Shih-Ting Lin, Shin-Puu Jeng | 2016-03-08 |