Issued Patents 2016
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9514986 | Device with capped through-substrate via structure | Yung-Chi Lin, Yen-Hung Chen, Yin Chen, Ebin Liao, Tsang-Jiuh Wu +1 more | 2016-12-06 |
| 9449898 | Semiconductor device having backside interconnect structure through substrate via and method of forming the same | Yung-Chi Lin, Hsin-Yu Chen, Ming-Tsu Chung, HsiaoYun Lo, Hong-Ye Shih +3 more | 2016-09-20 |
| 9425126 | Dummy structure for chip-on-wafer-on-substrate | Pei-Ching Kuo, Yi-Hsiu Chen, Jun-Lin Yeh, Yung-Chi Lin, Li-Han Hsu +2 more | 2016-08-23 |
| 9418933 | Through-substrate via formation with improved topography control | Yung-Chi Lin, Yi-Hsiu Chen, Wen-Chih Chiou | 2016-08-16 |
| 9373575 | TSV structures and methods for forming the same | Yung-Chi Lin, Hsin-Yu Chen, Wen-Chih Chiou, Tsang-Jiuh Wu, Jing-Cheng Lin | 2016-06-21 |
| 9343390 | TSV formation processes using TSV-last approach | Jing C. Lin, Yung-Chi Lin | 2016-05-17 |
| 9293418 | Backside through vias in a bonded structure | Weng-Jin Wu, Hung-Pin Chang, Wen-Chih Chiou, Chen-Hua Yu | 2016-03-22 |
| 9293366 | Through-substrate vias with improved connections | Jing-Cheng Lin | 2016-03-22 |
| 9263382 | Through substrate via structures and methods of forming the same | Tsang-Jiuh Wu, Yi-Hsiu Chen, Ebin Liao, Yuan-Hung Liu, Wen-Chih Chiou | 2016-02-16 |
| 9252110 | Interconnect structure and method of forming same | Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin +2 more | 2016-02-02 |