Issued Patents 2016
Showing 101–114 of 114 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9281254 | Methods of forming integrated circuit package | Chi-Hsi Wu, Wen-Chih Chiou, Hsiang-Fan Lee, Shih-Peng Tai, Tang-Jung Chiu | 2016-03-08 |
| 9275964 | Substrate contact opening | Jiun Yi Wu | 2016-03-01 |
| 9275925 | System and method for an improved interconnect structure | Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii, Tsung-Yuan Yu | 2016-03-01 |
| 9263407 | Method for manufacturing a plurality of metal posts | Yi-Li Hsiao, Su-Chun Yang, Chih-Hang Tung, Da-Yuan Shih | 2016-02-16 |
| 9263511 | Package with metal-insulator-metal capacitor and method of manufacturing the same | Shang-Yun Hou, Wen-Chih Chiou, Jui-Pin Hung, Der-Chyang Yeh, Chiung-Han Yeh | 2016-02-16 |
| 9263377 | POP structures with dams encircling air gaps and methods for forming the same | Tsung-Ding Wang, Chen-Shien Chen, Chung-Shi Liu, Jiun Yi Wu | 2016-02-16 |
| 9257506 | CMOS devices having dual high-mobility channels | Ding-Yuan Chen | 2016-02-09 |
| 9252135 | Packaged semiconductor devices and methods of packaging semiconductor devices | Chung-Shi Liu, Chih-Fan Huang, Chih-Wei Lin, Wei-Hung Lin, Ming-Da Cheng | 2016-02-02 |
| 9240349 | Interconnect structures for substrate | Wen-Chih Chiou, Shin-Puu Jeng, Tsang-Jiuh Wu | 2016-01-19 |
| 9240387 | Wafer-level chip scale package with re-workable underfill | Hsien-Wei Chen, Tsung-Ding Wang, Chien-Hsiun Lee, Hao-Yi Tsai, Mirng-Ji Lii | 2016-01-19 |
| 9236277 | Integrated circuit with a thermally conductive underfill and methods of forming same | Tien-I Bao | 2016-01-12 |
| 9230959 | FinFETs having dielectric punch-through stoppers | Cheng-Hung Chang, Chen-Nan Yeh | 2016-01-05 |
| 9230932 | Interconnect crack arrestor structure and methods | Da-Yuan Shih | 2016-01-05 |
| 9230902 | Interconnect structure for wafer level package | Jing-Cheng Lin, Nai-Wei Liu, Jui-Pin Hung, Shin-Puu Jeng | 2016-01-05 |