Issued Patents All Time
Showing 151–175 of 240 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9618712 | Optical bench on substrate and method of making the same | Ying-Hao Kuo, Wan-Yu Lee | 2017-04-11 |
| 9618572 | Testing of semiconductor chips with microbumps | Wei-Cheng Wu, Hsien-Pin Hu, Shin-Puu Jeng, Chen-Hua Yu, Chao-Hsiang Yang | 2017-04-11 |
| 9601443 | Test structure for seal ring quality monitor | Hao-Yi Tsai, Shih-Hsun Hsu, Shih-Cheng Chang, Hsien-Wei Chen, Chia-Lun Tsai +3 more | 2017-03-21 |
| 9589857 | Interposer test structures and methods | Tzuan-Horng Liu, Chen-Hua Yu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu +1 more | 2017-03-07 |
| 9581638 | Chip-on-wafer process control monitoring for chip-on-wafer-on-substrate packages | Wei-Cheng Wu, Li-Han Hsu, Sao-Ling Chiu, Shin-Puu Jeng, Chen-Hua Lin | 2017-02-28 |
| 9570324 | Method of manufacturing package system | Wei-Cheng Wu, Shin-Puu Jeng, Chen-Hua Yu | 2017-02-14 |
| 9570366 | Passivation layer for packaged chip | Shin-Puu Jeng, Wei-Cheng Wu, Chen-Hua Yu, Tzuan-Horng Liu, Tzu-Wei Chiu +1 more | 2017-02-14 |
| 9553053 | Bump structure for yield improvement | Tzu-Wei Chiu, Tzu-Yu Wang, Shin-Puu Jeng, Hsien-Wei Chen, Hung-An Teng +1 more | 2017-01-24 |
| 9530730 | Configurable routing for packaging applications | Chung-Yu Lu, Hsien-Pin Hu, Shin-Puu Jeng, Tzuan-Horng Liu, Shih-Wen Huang +1 more | 2016-12-27 |
| 9508666 | Packaging structures and methods with a metal pillar | Chen-Hua Yu, Shin-Puu Jeng, Kuo-Ching Hsu, Cheng-Chieh Hsieh, Ying-Ching Shih +3 more | 2016-11-29 |
| 9502380 | Three dimensional integrated circuits stacking approach | Jing-Cheng Lin | 2016-11-22 |
| 9502271 | Warpage control for flexible substrates | Chen-Hua Yu, Shih-Ting Lin, Jing-Cheng Lin, Szu-Wei Lu | 2016-11-22 |
| 9496235 | Pillar design for conductive bump | Cheng-Chieh Hsieh, Cheng-Lin Huang, Po-Hao Tsai, Jing-Cheng Lin, Shin-Puu Jeng | 2016-11-15 |
| 9462692 | Test structure and method of testing electrical characteristics of through vias | Wei-Cheng Wu, Hsien-Pin Hu, Jung Cheng Ko, Shin-Puu Jeng, Chen-Hua Yu +1 more | 2016-10-04 |
| 9412678 | Structure and method for 3D IC package | Der-Chyang Yeh, Shin-Puu Jeng, Chen-Hua Yu | 2016-08-09 |
| 9385091 | Reinforcement structure and method for controlling warpage of chip mounted on substrate | Chen-Hua Yu, Cheng-Chieh Hsieh, Tsung-Shu Lin | 2016-07-05 |
| 9385095 | 3D semiconductor package interposer with die cavity | Shin-Puu Jeng, Kim Hong Chen, Wensen Hung, Szu-Po Huang | 2016-07-05 |
| 9372206 | Testing of semiconductor chips with microbumps | Wei-Cheng Wu, Hsien-Pin Hu, Shin-Puu Jeng, Chen-Hua Yu, Chao-Hsiang Yang | 2016-06-21 |
| 9372951 | Semiconductor device design methods and conductive bump pattern enhancement methods | Tzu-Yu Wang, Wei-Cheng Wu, Kuo-Ching Hsu, Shin-Puu Jeng | 2016-06-21 |
| 9337123 | Thermal structure for integrated circuit package | Cheng-Chieh Hsieh, Way Lee Cheng, Shin-Puu Jeng | 2016-05-10 |
| 9305808 | Methods and apparatus of packaging with interposers | Chung-Yu Lu, Hsien-Pin Hu, Hsiao-Tsung Yen, Tzuan-Horng Liu, Shih-Wen Huang +1 more | 2016-04-05 |
| 9299649 | 3D packages and methods for forming the same | Tzu-Wei Chiu, Cheng-Hsien Hsieh, Hsien-Pin Hu, Kuo-Ching Hsu, Shin-Puu Jeng | 2016-03-29 |
| 9263511 | Package with metal-insulator-metal capacitor and method of manufacturing the same | Chen-Hua Yu, Wen-Chih Chiou, Jui-Pin Hung, Der-Chyang Yeh, Chiung-Han Yeh | 2016-02-16 |
| 9209156 | Three dimensional integrated circuits stacking approach | Jing-Cheng Len | 2015-12-08 |
| 9159673 | Forming interconnect structures using pre-ink-printed sheets | Jung Cheng Ko, Chi-Chun Hsieh, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu | 2015-10-13 |