Issued Patents All Time
Showing 126–150 of 240 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10163851 | Tri-layer CoWoS structure | Chen-Hua Yu, Yun-Han Lee | 2018-12-25 |
| 10163853 | Formation method of chip package | Wen-Hsin Wei, Chi-Hsi Wu, Chen-Hua Yu, Hsien-Pin Hu, Wei-Ming Chen | 2018-12-25 |
| 10153338 | Method of manufacturing a capacitor | Chun Hua Chang, Der-Chyang Yeh, Kuang-Wei Cheng, Yuan-Hung Liu, Wen-Chih Chiou +1 more | 2018-12-11 |
| 10153222 | Package structures and methods of forming the same | Chen-Hua Yu, Hsien-Pin Hu, Jing-Cheng Lin, Szu-Wei Lu, Wen-Hsin Wei +2 more | 2018-12-11 |
| 10153205 | Package with metal-insulator-metal capacitor and method of manufacturing the same | Chen-Hua Yu, Wen-Chih Chiou, Jui-Pin Hung, Der-Chyang Yeh, Chiung-Han Yeh | 2018-12-11 |
| 10090213 | Interposer test structures and methods | Tzuan-Horng Liu, Chen-Hua Yu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu +1 more | 2018-10-02 |
| 10056347 | Bump structure for yield improvement | Tzu-Wei Chiu, Tzu-Yu Wang, Shin-Puu Jeng, Hsien-Wei Chen, Hung-An Teng +1 more | 2018-08-21 |
| 9984981 | Packages with interposers and methods for forming the same | Sao-Ling Chiu, Kuo-Ching Hsu, Wei-Cheng Wu, Ping-Kang Huang, Shin-Puu Jeng +1 more | 2018-05-29 |
| 9978637 | Mechanism for forming patterned metal pad connected to multiple through silicon vias (TSVs) | Tzuan-Horng Liu, Shih-Wen Huang, Chung-Yu Lu, Hsien-Pin Hu, Shin-Puu Jeng | 2018-05-22 |
| 9953948 | Pillar design for conductive bump | Cheng-Chieh Hsieh, Cheng-Lin Huang, Po-Hao Tsai, Jing-Cheng Lin, Shin-Puu Jeng | 2018-04-24 |
| 9859235 | Underbump metallization structure | Yu-Wen Liu, Hao-Yi Tsai, Hsien-Wei Chen, Shin-Puu Jeng, Ying-Ju Chen +2 more | 2018-01-02 |
| 9818720 | Structure and formation method for chip package | Wen-Hsin Wei, Chi-Hsi Wu, Chen-Hua Yu, Hsien-Pin Hu, Wei-Ming Chen | 2017-11-14 |
| 9806058 | Chip package having die structures of different heights and method of forming same | Wen-Hsin Wei, Chi-Hsi Wu, Chen-Hua Yu, Hsien-Pin Hu, Wei-Ming Chen | 2017-10-31 |
| 9806038 | Reinforcement structure and method for controlling warpage of chip mounted on substrate | Chen-Hua Yu, Cheng-Chieh Hsieh, Tsung-Shu Lin | 2017-10-31 |
| 9786567 | Chip-on-wafer process control monitoring for chip-on-wafer-on-substrate packages | Wei-Cheng Wu, Li-Han Hsu, Sao-Ling Chiu, Shin-Puu Jeng, Chen-Hua Lin | 2017-10-10 |
| 9780072 | 3D semiconductor package interposer with die cavity | Shin-Puu Jeng, Kim Hong Chen, Wensen Hung, Szu-Po Huang | 2017-10-03 |
| 9760670 | Semiconductor device design methods and conductive bump pattern enhancement methods | Tzu-Yu Wang, Wei-Cheng Wu, Kuo-Ching Hsu, Shin-Puu Jeng | 2017-09-12 |
| 9741669 | Forming large chips through stitching | Wen-Hsin Wei, Hsien-Pin Hu, Wei-Ming Chen | 2017-08-22 |
| 9741638 | Thermal structure for integrated circuit package | Cheng-Chieh Hsieh, Shin-Puu Jeng, Way Lee Cheng | 2017-08-22 |
| 9691840 | Cylindrical embedded capacitors | An-Jhih Su, Chi-Chun Hsieh, Tzu-Yu Wang, Wei-Cheng Wu, Hsien-Pin Hu +2 more | 2017-06-27 |
| 9660016 | Method of manufacturing a capacitor | Chun Hua Chang, Der-Chyang Yeh, Kuang-Wei Cheng, Yuan-Hung Liu, Wen-Chih Chiou +1 more | 2017-05-23 |
| 9640490 | Through silicon via keep out zone formation method and system | Cheng-Chieh Hsieh, Hung-An Teng, Shin-Puu Jeng | 2017-05-02 |
| 9633869 | Packages with interposers and methods for forming the same | Sao-Ling Chiu, Kuo-Ching Hsu, Wei-Cheng Wu, Ping-Kang Huang, Shin-Puu Jeng +1 more | 2017-04-25 |
| 9627365 | Tri-layer CoWoS structure | Chen-Hua Yu, Yun-Han Lee | 2017-04-18 |
| 9627223 | Methods and apparatus of packaging with interposers | Chung-Yu Lu, Hsien-Pin Hu, Hsiao-Tsung Yen, Tzuan-Horng Liu, Shih-Wen Huang +1 more | 2017-04-18 |