Issued Patents 2017
Showing 1–25 of 109 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9852985 | Conductive terminal on integrated circuit | Yu-Chia Lai, Chang-Pin Huang, Chung-Shi Liu, Hsien-Ming Tu, Hung-Yi Kuo +3 more | 2017-12-26 |
| 9847317 | Methods of packaging semiconductor devices and packaged semiconductor devices | Chung-Shi Liu, Meng-Tse Chen, Hui-Min Huang, Chih-Fan Huang, Ming-Da Cheng | 2017-12-19 |
| 9842788 | Underfill control structures and method | Ying-Ju Chen, An-Jhih Su, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu | 2017-12-12 |
| 9842817 | Solder bump stretching method and device for performing the same | Su-Chun Yang, Yi-Li Hsiao, Chih-Hang Tung | 2017-12-12 |
| 9842815 | Semiconductor device and method of manufacture | Tin-Hao Kuo, Chung-Shi Liu, Hao-Yi Tsai | 2017-12-12 |
| 9842826 | Semiconductor device and method of manufacture | Jing-Cheng Lin, Po-Hao Tsai | 2017-12-12 |
| 9843106 | Integrated fan out antenna and method of forming the same | Chuei-Tang Wang, Jeng-Shieh Hsieh, Chung-Hao Tsai, Monsen Liu | 2017-12-12 |
| 9842823 | Chip-stacking apparatus having a transport device configured to transport a chip onto a substrate | HsiaoYun Lo, Yi-Hsiu Chen, Wen-Chih Chiou | 2017-12-12 |
| 9837370 | Bump structures for multi-chip packaging | Jing-Cheng Lin | 2017-12-05 |
| 9831224 | Solution for reducing poor contact in info packages | Jing-Cheng Lin, Szu-Wei Lu, Shih-Ting Lin, Shin-Puu Jeng | 2017-11-28 |
| 9831148 | Integrated fan-out package including voltage regulators and methods forming same | Chih-Yuan Chang, Chuei-Tang Wang, Jeng-Shien Hsieh | 2017-11-28 |
| 9824902 | Integrated fan-out package and method of fabricating the same | Hao-Cheng Hou, Chien-Hsun Lee, Chung-Shi Liu, Jung Wei Cheng, Ping-Kang Huang +2 more | 2017-11-21 |
| 9818720 | Structure and formation method for chip package | Wen-Hsin Wei, Chi-Hsi Wu, Hsien-Pin Hu, Shang-Yun Hou, Wei-Ming Chen | 2017-11-14 |
| 9812427 | Package on-package (PoP) structure including stud bulbs | Mirng-Ji Lii, Chung-Shi Liu, Ming-Da Cheng | 2017-11-07 |
| 9812337 | Integrated circuit package pad and methods of forming | Hsien-Wei Chen, Chi-Hsi Wu, Der-Chyang Yeh, An-Jhih Su, Wei-Yu Chen | 2017-11-07 |
| 9806055 | Chip-on-wafer package and method of forming same | Ming-Fa Chen, Sung-Feng Yeh | 2017-10-31 |
| 9806038 | Reinforcement structure and method for controlling warpage of chip mounted on substrate | Shang-Yun Hou, Cheng-Chieh Hsieh, Tsung-Shu Lin | 2017-10-31 |
| 9806058 | Chip package having die structures of different heights and method of forming same | Wen-Hsin Wei, Chi-Hsi Wu, Hsien-Pin Hu, Shang-Yun Hou, Wei-Ming Chen | 2017-10-31 |
| 9802349 | Wafer level transfer molding and apparatus for performing the same | Bor-Ping Jang, Yeong-Jyh Lin, Chien Ling Hwang, Chung-Shi Liu, Meng-Tse Chen +1 more | 2017-10-31 |
| 9799694 | Backside through vias in a bonded structure | Weng-Jin Wu, Ku-Feng Yang, Hung-Pin Chang, Wen-Chih Chiou | 2017-10-24 |
| 9799625 | Semiconductor structure and manufacturing method thereof | Alexander Kalnitsky, Yi-Yang Lei, Hsi-Ching Wang, Cheng-Yu Kuo, Tsung Lung Huang +9 more | 2017-10-24 |
| 9793140 | Staggered via redistribution layer (RDL) for a package and a method for forming the same | Chung-Shi Liu, Hung-Jui Kuo | 2017-10-17 |
| 9793192 | Formation of through via before contact processing | Wen-Chih Chiou, Weng-Jin Wu | 2017-10-17 |
| 9793230 | Semiconductor structure and method of forming | Yu-Hsiang Hu, Hung-Jui Kuo | 2017-10-17 |
| 9786599 | Package structures and method of forming the same | An-Jhih Su | 2017-10-10 |