Issued Patents 2017
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9852985 | Conductive terminal on integrated circuit | Yu-Chia Lai, Chen-Hua Yu, Chung-Shi Liu, Hsien-Ming Tu, Hung-Yi Kuo +3 more | 2017-12-26 |
| 9812434 | Hollow metal pillar packaging scheme | Hsien-Ming Tu, Hsien-Wei Chen, Tung-Liang Shao, Ching-Jung Yang, Yu-Chia Lai | 2017-11-07 |
| 9799615 | Package structures having height-adjusted molding members and methods of forming the same | Chung-Shi Liu, Hsien-Ming Tu, Hung-Yi Kuo, Hao-Yi Tsai, Shih-Wei Liang +2 more | 2017-10-24 |
| 9786618 | Semiconductor structure and manufacturing method thereof | Hsien-Ming Tu, Ching-Jung Yang, Shih-Wei Liang, Hung-Yi Kuo, Yu-Chia Lai +3 more | 2017-10-10 |
| 9748212 | Shadow pad for post-passivation interconnect structures | Shih-Wei Liang, Bor-Rung Su, Chien-Chia Chiu, Hsien-Ming Tu, Chun-Hung Lin +1 more | 2017-08-29 |
| 9679883 | Hollow metal pillar packaging scheme | Hsien-Ming Tu, Hsien-Wei Chen, Tung-Liang Shao, Ching-Jung Yang, Yu-Chia Lai | 2017-06-13 |
| 9640498 | Integrated fan-out (InFO) package structures and methods of forming same | Chen-Hua Yu, Ching-Jung Yang, Chung-Shi Liu, Hsien-Ming Tu, Hung-Yi Kuo +3 more | 2017-05-02 |
| 9627332 | Integrated circuit structure and seal ring structure | Shih-Wei Liang, Hsien-Ming Tu, Ching-Jung Yang, Yu-Chia Lai | 2017-04-18 |
| 9559044 | Package with solder regions aligned to recesses | Ching-Jung Yang, Hsien-Wei Chen, Hsien-Ming Tu, Yu-Chia Lai, Tung-Liang Shao | 2017-01-31 |