Issued Patents 2017
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9847315 | Packages, packaging methods, and packaged semiconductor devices | Shih-Ting Lin, Jui-Pin Hung, Jing-Cheng Lin | 2017-12-19 |
| 9831224 | Solution for reducing poor contact in info packages | Jing-Cheng Lin, Chen-Hua Yu, Shih-Ting Lin, Shin-Puu Jeng | 2017-11-28 |
| 9818697 | Semiconductor package manufacturing method | Jing-Cheng Lin, Po-Hao Tsai, Ying-Ching Shih | 2017-11-14 |
| 9793187 | 3D packages and methods for forming the same | Shih-Ting Lin, Kung-Chen Yeh, Jing-Cheng Lin | 2017-10-17 |
| 9773724 | Semiconductor devices, methods of manufacture thereof, and semiconductor device packages | I-Ting Chen, Ying-Ching Shih, Po-Hao Tsai, Jing-Cheng Lin | 2017-09-26 |
| 9704825 | Chip packages and methods of manufacture thereof | Chih-Wei Wu, Jing-Cheng Lin, Ying-Ching Shih | 2017-07-11 |
| 9679783 | Molding wafer chamber | Jing-Cheng Lin, Chin-Chuan Chang, Jui-Pin Hung, Shin-Puu Jeng, Chen-Hua Yu | 2017-06-13 |
| 9662872 | De-bonding and cleaning process and system | Ying-Ching Shih, Jing-Cheng Lin | 2017-05-30 |
| 9633954 | Methods of manufacturing an integrated circuit having stress tuning layer | Shin-Puu Jeng, Clinton Chao | 2017-04-25 |
| 9627346 | Underfill pattern with gap | Feng-Cheng Hsu, Hou-Ju Huang, Jing-Cheng Lin | 2017-04-18 |
| 9620430 | Sawing underfill in packaging processes | Ying-Da Wang, Li-Chung Kuo, Jing-Cheng Lin | 2017-04-11 |
| 9583461 | Probing chips during package formation | Jing-Cheng Lin | 2017-02-28 |
| 9570421 | Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure | Chih-Wei Wu, Ying-Ching Shih, Jing-Cheng Lin | 2017-02-14 |