Issued Patents 2017
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9847315 | Packages, packaging methods, and packaged semiconductor devices | Shih-Ting Lin, Szu-Wei Lu, Jing-Cheng Lin | 2017-12-19 |
| 9748189 | Multi-chip package structure and method of forming same | Chen-Hua Yu, Jing-Cheng Lin, Der-Chyang Yeh | 2017-08-29 |
| 9704826 | Chip on package structure and method | Chen-Hua Yu, Der-Chyang Yeh, Kuo-Chung Yee | 2017-07-11 |
| 9691706 | Multi-chip fan out package and methods of forming the same | Chen-Hua Yu, Jing-Cheng Lin | 2017-06-27 |
| 9679783 | Molding wafer chamber | Jing-Cheng Lin, Chin-Chuan Chang, Szu-Wei Lu, Shin-Puu Jeng, Chen-Hua Yu | 2017-06-13 |
| 9673098 | Methods of packaging semiconductor devices and structures thereof | Jing-Cheng Lin, Yi-Hang Lin, Tsan-Hua Tung | 2017-06-06 |
| 9673181 | Package on package (PoP) bonding structures | Jing-Cheng Lin, Po-Hao Tsai | 2017-06-06 |
| 9662812 | Methods for molding integrated circuits | Chih-Hao Chen, Hsien-Wen Liu, Yi-Lin Tsai, Jing-Cheng Lin | 2017-05-30 |
| 9633895 | Integrated fan-out structure with guiding trenches in buffer layer | Po-Hao Tsai, Feng-Cheng Hsu, Li-Hui Cheng, Jing-Cheng Lin | 2017-04-25 |
| 9595510 | Structure and formation method for chip package | Cheng-Lin Huang, Hsien-Wen Liu, Shin-Puu Jeng | 2017-03-14 |
| 9583424 | Integrated circuit structure and method for reducing polymer layer delamination | Jing-Cheng Lin, Hsien-Wen Liu, Min-Chen Lin | 2017-02-28 |
| 9576910 | Semiconductor packaging structure and manufacturing method thereof | Chen-Hua Yu, Ming-Da Cheng | 2017-02-21 |
| 9570401 | Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices | Po-Hao Tsai, Jing-Cheng Lin | 2017-02-14 |
| 9553000 | Interconnect structure for wafer level package | Chen-Hua Yu, Jing-Cheng Lin, Nai-Wei Liu, Shin-Puu Jeng | 2017-01-24 |