Issued Patents 2017
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9842790 | Conductive line system and process | Yu Yi Huang, Chung-Shi Liu | 2017-12-12 |
| 9837278 | Wafer level chip scale package and method of manufacturing the same | Yu-Hsiang Hu, Wei-Yu Chen, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu | 2017-12-05 |
| 9793230 | Semiconductor structure and method of forming | Chen-Hua Yu, Yu-Hsiang Hu | 2017-10-17 |
| 9793140 | Staggered via redistribution layer (RDL) for a package and a method for forming the same | Chen-Hua Yu, Chung-Shi Liu | 2017-10-17 |
| 9786617 | Chip packages and methods of manufacture thereof | Zi-Jheng Liu, Chen-Cheng Kuo, Chung-Shi Liu, Yu-Hsiang Hu | 2017-10-10 |
| 9765289 | Cleaning methods and compositions | Hui-Jung Tsai, Chung-Shi Liu | 2017-09-19 |
| 9741586 | Method of fabricating package structures | Yu-Hsiang Hu, Chung-Shi Liu, Sih-Hao Liao | 2017-08-22 |
| 9659805 | Fan-out interconnect structure and methods forming the same | Yu-Hsiang Hu, Chung-Shi Liu, Ming-Da Cheng | 2017-05-23 |
| 9601355 | Via structure for packaging and a method of forming | Ming-Che Ho, Yi-Wen Wu, Chien Ling Hwang, Chung-Shi Liu | 2017-03-21 |
| 9576874 | Semiconductor devices and methods of manufacture thereof | Yu-Feng Chen, Kai-Chiang Wu, Chun-Lin Lu | 2017-02-21 |
| 9570413 | Packages with solder ball revealed through laser | Yu-Hsiang Hu, Wei-Yu Chen, Ming-Da Cheng, Chung-Shi Liu | 2017-02-14 |
| 9548283 | Package redistribution layer structure and method of forming same | Tsung-Shu Lin, Yi-Wen Wu | 2017-01-17 |