Issued Patents All Time
Showing 51–75 of 107 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9888528 | Substrate support with multiple heating zones | Tomoharu Matsushita, Jallepally Ravi, Aravind Kamath, Xiaoxiong Yuan, Manjunatha Koppa | 2018-02-06 |
| 9865437 | High conductance process kit | Bonnie T. Chia | 2018-01-09 |
| 9831117 | Self-aligned double spacer patterning process | Yung-Hsu Wu, Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue | 2017-11-28 |
| 9818585 | In situ plasma clean for removal of residue from pedestal surface without breaking vacuum | Richard Green, Shambhu N. Roy, Puneet Bajaj, David H. Loo | 2017-11-14 |
| 9773676 | Lithography using high selectivity spacers for pitch reduction | Yu-Sheng Chang, Chung-Ju Lee, Hai-Ching Chen, Hsiang-Huan Lee, Ming-Feng Shieh +5 more | 2017-09-26 |
| 9768031 | Semiconductor device manufacturing methods | Tsung-Min Huang, Chung-Ju Lee | 2017-09-19 |
| 9735052 | Metal lines for interconnect structure and method of manufacturing same | Carlos H. Diaz, Chung-Ju Lee, Shau-Lin Shue, Tien-I Bao, Yung-Hsu Wu +1 more | 2017-08-15 |
| 9685368 | Interconnect structure having an etch stop layer over conductive lines | Chung-Ju Lee, Shau-Lin Shue, Tien-I Bao | 2017-06-20 |
| 9653349 | Semiconductor integrated circuit with nano gap | Chieh-Han Wu, Chung-Ju Lee, Shau-Lin Shue | 2017-05-16 |
| 9627256 | Integrated circuit interconnects and methods of making same | Chung-Ju Lee, Bo-Jiun Lin, Hsien-Chang Wu | 2017-04-18 |
| 9627215 | Structure and method for interconnection | Chien-Hua Huang, Chung-Ju Lee, Cherng-Shiaw Tsai | 2017-04-18 |
| 9613846 | Pad design for electrostatic chuck surface | Govinda Raj, Robert T. Hirahara, Kadthala Ramaya Narendrnath, Manjunatha Koppa, Ross Marshall | 2017-04-04 |
| 9607850 | Self-aligned double spacer patterning process | Yung-Hsu Wu, Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue | 2017-03-28 |
| 9608549 | Electrostatic chuck | Vijay D. Parkhe, Steven V. Sansoni | 2017-03-28 |
| 9595464 | Apparatus and method for reducing substrate sliding in process chambers | Sriskantharajah Thirunavukarasu, Kirankumar Neelasandra SAVANDAIAH, Kai Liang Liew | 2017-03-14 |
| 9589890 | Method for interconnect scheme | Hsin-Chieh Yao, Carlos H. Diaz, Chung-Ju Lee, Chien-Hua Huang, Hsi-Wen Tien +3 more | 2017-03-07 |
| 9576814 | Method of spacer patterning to form a target integrated circuit pattern | Chieh-Han Wu, Chung-Ju Lee, Ming-Feng Shieh, Ru-Gun Liu, Shau-Lin Shue +1 more | 2017-02-21 |
| 9564397 | Interconnect structure and method of forming the same | Chung-Ju Lee, Hai-Ching Chen, Shau-Lin Shue, Tien-I Bao | 2017-02-07 |
| 9502261 | Spacer etching process for integrated circuit design | Ru-Gun Liu, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee, Jyu-Horng Shieh +6 more | 2016-11-22 |
| 9490205 | Integrated circuit interconnects and methods of making same | Chung-Ju Lee, Tsung-Jung Tsai, Hsiang-Huan Lee, Ming-Han Lee | 2016-11-08 |
| 9478430 | Method of semiconductor integrated circuit fabrication | Hsin-Chieh Yao, Chung-Ju Lee, Tien-I Bao | 2016-10-25 |
| 9431297 | Method of forming an interconnect structure for a semiconductor device | Yung-Hsu Wu, Yu-Sheng Chang, Chia-Tien Wu, Chung-Ju Lee, Yung-Sung Yen +4 more | 2016-08-30 |
| 9412651 | Air-gap formation in interconnect structures | Chung-Ju Lee, Tien-I Bao | 2016-08-09 |
| 9396933 | PVD buffer layers for LED fabrication | Mingwei Zhu, Rongjun Wang, Nag B. Patibandia, Xianmin Tang, Vivek Agrawal +5 more | 2016-07-19 |
| 9355865 | Semiconductor patterning | Chung-Ju Lee, Tsung-Jung Tsai, Yu-Sheng Chang | 2016-05-31 |