Issued Patents All Time
Showing 301–325 of 482 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10886217 | Integrated circuit device with back-side interconnection to deep source/drain semiconductor | Patrick Morrow, Mauro J. Kobrinsky, Mark Bohr, Rishabh Mehandru | 2021-01-05 |
| 10879241 | Techniques for controlling transistor sub-fin leakage | Glenn A. Glass, Prashant Majhi, Anand S. Murthy, Daniel B. Aubertine, Heidi M. Meyer +2 more | 2020-12-29 |
| 10879365 | Transistors with non-vertical gates | Cheng-Ying Huang, Sean T. Ma, Willy Rachmady, Gilbert Dewey, Matthew V. Metz +3 more | 2020-12-29 |
| 10879353 | Selective germanium P-contact metalization through trench | Glenn A. Glass, Anand S. Murthy | 2020-12-29 |
| 10868233 | Approaches for strain engineering of perpendicular magnetic tunnel junctions (pMTJs) and the resulting structures | Daniel G. Ouellette, Christopher J. Wiegand, MD Tofizur Rahman, Brian Maertz, Oleg Golonzka +5 more | 2020-12-15 |
| 10861851 | Wrap-around trench contact structure and methods of fabrication | Joseph M. Steigerwald, Oleg Golonzka | 2020-12-08 |
| 10854752 | High mobility strained channels for fin-based NMOS transistors | Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Glenn A. Glass, Anand S. Murthy +1 more | 2020-12-01 |
| 10847631 | Gate-all-around (GAA) transistors with nanowires on an isolation pedestal | Annalisa Cappellani, Abhijit Jayant Pethe, Harry Gomez | 2020-11-24 |
| 10847714 | PSTTM device with multi-layered filter stack | Kaan Oguz, Kevin P. O'Brien, Christopher J. Wiegand, MD Tofizur Rahman, Brian S. Doyle +3 more | 2020-11-24 |
| 10847635 | Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices | Rishabh Mehandru, Patrick Morrow, Ranjith Kumar, Cory E. Weber, Seiyon Kim +1 more | 2020-11-24 |
| 10818793 | Indium-rich NMOS transistor channels | Chandra S. Mohapatra, Anand S. Murthy, Glenn A. Glass, Willy Rachmady, Jack T. Kavalieros +3 more | 2020-10-27 |
| 10811595 | Techniques for forming logic including integrated spin-transfer torque magnetoresistive random-access memory | Kevin J. Lee, Oleg Golonzka, Ruth A. Brain, Yih Wang | 2020-10-20 |
| 10804357 | Integration methods to fabricate internal spacers for nanowire devices | Seiyon Kim, Kelin J. Kuhn, Anand S. Murthy, Mark Armstrong, Rafael Rios +2 more | 2020-10-13 |
| 10804460 | Device, system and method for improved magnetic anisotropy of a magnetic tunnel junction | MD Tofizur Rahman, Christopher J. Wiegand, Brian Maertz, Daniel G. Ouellette, Kevin P. O'Brien +6 more | 2020-10-13 |
| 10797150 | Differential work function between gate stack metals to reduce parasitic capacitance | Sean T. Ma, Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Gilbert Dewey +3 more | 2020-10-06 |
| 10790354 | Self-aligned gate edge and local interconnect | Milton Clair Webb, Mark Bohr, Szuya S. Liao | 2020-09-29 |
| 10777656 | Fin cut and fin trim isolation for advanced integrated circuit structure fabrication | Byron Ho, Curtis W. Ward, Michael L. Hattendorf, Christopher P. Auth | 2020-09-15 |
| 10770593 | Beaded fin transistor | Gilbert Dewey, Willy Rachmady, Jack T. Kavalieros, Matthew V. Metz, Anand S. Murthy +1 more | 2020-09-08 |
| 10770651 | Perpendicular spin transfer torque memory (PSTTM) devices with enhanced perpendicular anisotropy and methods to form same | MD Tofizur Rahman, Christopher J. Wiegand, Kaan Oguz, Daniel G. Ouellette, Brian Maertz +4 more | 2020-09-08 |
| 10770458 | Nanowire transistor device architectures | Rishabh Mehandru, Szuya S. Liao, Seiyon Kim | 2020-09-08 |
| 10756204 | Fin trim isolation with single gate spacing for advanced integrated circuit structure fabrication | Byron Ho, Michael L. Hattendorf, Christopher P. Auth | 2020-08-25 |
| 10755984 | Replacement channel etch for high quality interface | Glenn A. Glass, Ying-Feng PANG, Nabil G. Mistkawi, Anand S. Murthy, Huang-Lin Chao | 2020-08-25 |
| 10749032 | Techniques for forming transistors including group III-V material nanowires using sacrificial group IV material layers | Chandra S. Mohapatra, Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Willy Rachmady +2 more | 2020-08-18 |
| 10748900 | Fin-based III-V/SI or GE CMOS SAGE integration | Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Chandra S. Mohapatra, Jack T. Kavalieros +1 more | 2020-08-18 |
| 10732217 | Ferromagnetic resonance testing of buried magnetic layers of whole wafer | Kevin P. O'Brien, Kaan Oguz, Christopher J. Wiegand, Mark L. Doczy, Brian S. Doyle +2 more | 2020-08-04 |