Issued Patents All Time
Showing 26–50 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7955926 | Structure and method to control oxidation in high-k gate structures | Wesley C. Natzle, Renee T. Mo, Rashmi Jha, Kathryn T. Schonenberg | 2011-06-07 |
| 7838390 | Methods of forming integrated circuit devices having ion-cured electrically insulating layers therein | Jun Jung Kim, Joo-chan Kim, Jae-eon Park, Zhao Lun, Johnny Widodo +2 more | 2010-11-23 |
| 7804136 | Method of forming nitride films with high compressive stress for improved PFET device performance | Ronald P. Bourque, Nancy R. Klymko, Anita Madan, Michael C. Smits, Roy H. Tilghman +2 more | 2010-09-28 |
| 7651947 | Mask forming and implanting methods using implant stopping layer and mask so formed | Katherina Babich, Todd C. Bailey, Ryan P. Deschner | 2010-01-26 |
| 7491660 | Method of forming nitride films with high compressive stress for improved PFET device performance | Ronald P. Bourque, Nancy R. Klymko, Anita Madan, Michael C. Smits, Roy H. Tilghman +2 more | 2009-02-17 |
| 7485573 | Process of making a semiconductor device using multiple antireflective materials | Marie Angelopoulos, Katherina Babich, Sean D. Burns, Allen H. Gabor, Scott D. Halle +2 more | 2009-02-03 |
| 7462527 | Method of forming nitride films with high compressive stress for improved PFET device performance | Ronald P. Bourque, Nancy R. Klymko, Anita Madan, Michael C. Smits, Roy H. Tilghman +2 more | 2008-12-09 |
| 7372158 | HDP-based ILD capping layer | Yun-Yu Wang, Chung-Ping Eng, Matthew Nicholls | 2008-05-13 |
| 7326651 | Method for forming damascene structure utilizing planarizing material coupled with compressive diffusion barrier material | Heidi Baks, Richard A. Bruff, Allan Upham | 2008-02-05 |
| 7179760 | Bilayer cap structure including HDP/bHDP films for conductive metallization and method of making same | Thomas Houghton, Michael F. Lofaro, Jeffery B. Maxson, Ann McDonald, Yun-Yu Wang +2 more | 2007-02-20 |
| 7138717 | HDP-based ILD capping layer | Yun-Yu Wang, Chung-Ping Eng, Matthew Nicholls | 2006-11-21 |
| 7084079 | Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications | Daniel C. Edelstein, Gill Yong Lee | 2006-08-01 |
| 6946345 | Self-aligned buried strap process using doped HDP oxide | Jochen Beintner, Wolfgang Bergner, Andreas Knorr, Rolf Weis | 2005-09-20 |
| 6911378 | Stabilization of fluorine-containing dielectric materials in a metal insulator wiring structure | Kenneth M. Davis, John A. Fitzsimmons, David L. Rath, Daewon Yang | 2005-06-28 |
| 6740539 | Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates | Prakash Dev, David M. Dobuzinsky, Daniel C. Edelstein, Gill Yong Lee, Kia-Seng Low +3 more | 2004-05-25 |
| 6667504 | Self-aligned buried strap process using doped HDP oxide | Jochen Beintner, Wolfgang Bergner, Andreas Knorr, Rolf Weis | 2003-12-23 |
| 6570256 | Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates | Prakash Dev, David M. Dobuzinsky, Daniel C. Edelstein, Gill Yong Lee, Kia-Seng Low +3 more | 2003-05-27 |
| 6548357 | Modified gate processing for optimized definition of array and logic devices on same chip | Mary E. Weybright, Gary B. Bronner, Ramachandra Divakaruni, Jeffrey P. Gambino, Peter D. Hoh +1 more | 2003-04-15 |
| 6531412 | Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications | Daniel C. Edelstein, Gill Yong Lee | 2003-03-11 |
| 6500772 | Methods and materials for depositing films on semiconductor substrates | Ashima B. Chakravarti, Chester T. Dziobkowski, Thomas Ivers, Paul C. Jamison, Frank V. Liucci | 2002-12-31 |
| 6486015 | Low temperature carbon rich oxy-nitride for improved RIE selectivity | Nirmal Chaudhary | 2002-11-26 |
| 6429149 | Low temperature LPCVD PSG/BPSG process | Ashima B. Chakravarti, Laertis Economikos, Byeongju Park | 2002-08-06 |
| 6403423 | Modified gate processing for optimized definition of array and logic devices on same chip | Mary E. Weybright, Gary B. Bronner, Ramachandra Divakaruni, Jeffrey P. Gambino, Peter D. Hoh +1 more | 2002-06-11 |
| 6335261 | Directional CVD process with optimized etchback | Wesley C. Natzle, Laertis Economikos, Thomas Ivers, George D. Papasouliotis | 2002-01-01 |
| 6274440 | Manufacturing of cavity fuses on gate conductor level | Kenneth C. Arndt, Axel Brintzinger, Donna R. Cote, Chandrasekhar Narayan, Ravikumar Ramachandran +2 more | 2001-08-14 |