Issued Patents All Time
Showing 276–300 of 584 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8298937 | Interconnect structure fabricated without dry plasma etch processing | Maxime Darnon, Elbert E. Huang, Qinghuang Lin | 2012-10-30 |
| 8298930 | Undercut-repair of barrier layer metallurgy for solder bumps and methods thereof | Charles L. Arvin, Timothy H. Daubenspeck, Christopher D. Muzzy, Wolfgang Sauter | 2012-10-30 |
| 8298917 | Process for wet singulation using a dicing singulation structure | Paul S. Andry, Timothy H. Daubenspeck, Edmund J. Sprogis, Cornelia K. Tsang | 2012-10-30 |
| 8298860 | Methods for forming a bonded semiconductor substrate including a cooling mechanism | Anthony K. Stamper | 2012-10-30 |
| 8294270 | Copper alloy via bottom liner | Daniel C. Edelstein, Edward C. Cooney, III, John A. Fitzsimmons, Anthony K. Stamper | 2012-10-23 |
| 8293638 | Method of fabricating damascene structures | Peter J. Lindgren, Anthony K. Stamper | 2012-10-23 |
| 8242012 | Integrated circuit structure incorporating a conductor layer with both top surface and sidewall passivation and a method of forming the integrated circuit structure | Timothy H. Daubenspeck, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan | 2012-08-14 |
| 8238032 | Variable focus point lens | John J. Ellis-Monaghan, Kirk D. Peterson, Jed H. Rankin | 2012-08-07 |
| 8236655 | Fuse link structures using film stress for programming and methods of manufacture | Karl W. Barth, Tom C. Lee, Kevin S. Petrarca | 2012-08-07 |
| 8236683 | Conductor structure including manganese oxide capping layer | Stephen E. Luce | 2012-08-07 |
| 8237279 | Collar structure around solder balls that connect semiconductor die to semiconductor chip package substrate | Timothy H. Daubenspeck, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan | 2012-08-07 |
| 8232215 | Spacer linewidth control | James A. Culp, John J. Ellis-Monaghan, Kirk D. Peterson, Jed H. Rankin | 2012-07-31 |
| 8232612 | Semiconductor transistors having high-K gate dielectric layers, metal gate electrode regions, and low fringing capacitances | James W. Adkisson, Michael P. Chudzik, Renee T. Mo, Naim Moumen | 2012-07-31 |
| 8232651 | Bond pad for wafer and package for CMOS imager | James W. Adkisson, Mark D. Jaffe, Richard L. Rassel | 2012-07-31 |
| 8232190 | Three dimensional vertical E-fuse structures and methods of manufacturing the same | Kerry Bernstein, Timothy J. Dalton, Mark D. Jaffe, Stephen E. Luce, Anthony K. Stamper | 2012-07-31 |
| 8227874 | Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes | James W. Adkisson, Michael P. Chudzik, Hongwen Yan | 2012-07-24 |
| 8227333 | Ni plating of a BLM edge for Pb-free C4 undercut control | Timothy H. Daubenspeck, Christopher D. Muzzy, Wolfgang Sauter | 2012-07-24 |
| 8217259 | Enhanced efficiency solar cells and method of manufacture | Scott W. Jones, Robert K. Leidy, Mark J. Pouliot | 2012-07-10 |
| 8212357 | Combination via and pad structure for improved solder bump electromigration characteristics | Timothy H. Daubenspeck, Timothy D. Sullivan | 2012-07-03 |
| 8207609 | Optically transparent wires for secure circuits and methods of making same | Stephen P. Ayotte, Timothy D. Sullivan, Kimball M. Watson | 2012-06-26 |
| 8198133 | Structures and methods to improve lead-free C4 interconnect reliability | Timothy H. Daubenspeck, Paul F. Fortier, Christopher D. Muzzy, David L. Questad, Wolfgang Sauter +1 more | 2012-06-12 |
| 8193563 | High power device isolation and integration | Steven H. Voldman, Michael J. Zierak | 2012-06-05 |
| 8178434 | On-chip embedded thermal antenna for chip cooling | Fen Chen, Alvin W. Strong | 2012-05-15 |
| 8168474 | Self-dicing chips using through silicon vias | James W. Adkisson, Panglijen Candra, Thomas J. Dunbar, Mark D. Jaffe, Robert K. Leidy +1 more | 2012-05-01 |
| 8164188 | Methods of forming solder connections and structure thereof | Timothy H. Daubenspeck, Christopher D. Muzzy, Wolfgang Sauter | 2012-04-24 |