Issued Patents All Time
Showing 151–175 of 240 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6475929 | Method of manufacturing a semiconductor structure with treatment to sacrificial stop layer producing diffusion to an adjacent low-k dielectric layer lowering the constant | Calvin T. Gabriel, Suzette K. Pangrle, Lynne A. Okada | 2002-11-05 |
| 6472317 | Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers | Jerry Cheng, Simon S. Chan, Todd P. Lukanc | 2002-10-29 |
| 6465361 | Method for preventing damage of low-k dielectrics during patterning | Lu You, Steve Avanzino | 2002-10-15 |
| 6465340 | Via filled dual damascene structure with middle stop layer and method for making the same | Lynne A. Okada, Ramkumar Subramanian, Calvin T. Gabriel | 2002-10-15 |
| 6465343 | Method for forming backend interconnect with copper etching and ultra low-k dielectric materials | — | 2002-10-15 |
| 6465889 | Silicon carbide barc in dual damascene processing | Ramkumar Subramanian, Lynne A. Okada, Calvin T. Gabriel, Darrell M. Erb | 2002-10-15 |
| 6454916 | Selective electroplating with direct contact chemical polishing | Steven C. Avanzino, Darrell M. Erb | 2002-09-24 |
| 6444573 | Method of making a slot via filled dual damascene structure with a middle stop layer | Lynne A. Okada, Ramkumar Subramanian, Calvin T. Gabriel | 2002-09-03 |
| 6444530 | Process for fabricating an integrated circuit with a self-aligned contact | Hung-Sheng Chen, Unsoon Kim, Yu Sun, Chi Chang, Mark T. Ramsbey +4 more | 2002-09-03 |
| 6440640 | Thin resist with transition metal hard mask for via etch application | Chih-Yuh Yang, Christopher F. Lyons, Harry J. Levinson, Khanh B. Nguyen, Scott A. Bell | 2002-08-27 |
| 6436766 | Process for fabricating high density memory cells using a polysilicon hard mask | Bharath Rangarajan, David K. Foote, Dawn Hopper, Stephen Keetai Park, Jack F. Thomas +2 more | 2002-08-20 |
| 6429116 | Method of fabricating a slot dual damascene structure without middle stop layer | Lynne A. Okada, Ramkumar Subramanian, Calvin T. Gabriel | 2002-08-06 |
| 6423612 | Method of fabricating a shallow trench isolation structure with reduced topography | Wenge Yang, John Jianshi Wang | 2002-07-23 |
| 6424039 | Dual damascene process using sacrificial spin-on materials | Bhanwar Singh, James Kai | 2002-07-23 |
| 6420752 | Semiconductor device with self-aligned contacts using a liner oxide layer | Minh Van Ngo, Yu Sun, Mark T. Ramsbey, Chi Chang, Angela T. Hui +1 more | 2002-07-16 |
| 6416620 | Method of repulping repulpable and recyclable moisture resistant coated articles | Radi Narancic, Gary M. Freeman, Eve De LaVega-Irvine | 2002-07-09 |
| 6417090 | Damascene arrangement for metal interconnection using low k dielectric constant materials for etch stop layer | Lu You | 2002-07-09 |
| 6399446 | Process for fabricating high density memory cells using a metallic hard mask | Bharath Rangarajan, David K. Foote, Dawn Hopper, Stephen Keetai Park, Jack F. Thomas +2 more | 2002-06-04 |
| 6399480 | Methods and arrangements for insulating local interconnects for improved alignment tolerance and size reduction | William G. En, Darin A. Chan, David K. Foote, Minh Van Ngo | 2002-06-04 |
| 6400030 | Self-aligning vias for semiconductors | Robin Cheung, Mark S. Chang, Richard J. Huang, Angela T. Hui | 2002-06-04 |
| 6391766 | Method of making a slot via filled dual damascene structure with middle stop layer | Lynne A. Okada, Ramkumar Subramanian, Calvin T. Gabriel | 2002-05-21 |
| 6383919 | Method of making a dual damascene structure without middle stop layer | Lynne A. Okada, Ramkumar Subramanian, Calvin T. Gabriel | 2002-05-07 |
| 6380091 | Dual damascene arrangement for metal interconnection with oxide dielectric layer and low K dielectric constant layer | Jerry Cheng, Darrell M. Erb | 2002-04-30 |
| 6376389 | Method for eliminating anti-reflective coating in semiconductors | Ramkumar Subramanian, Minh Van Ngo, Kashmir Sahota, YongZhong Hu, Hiroyuki Kinoshita +1 more | 2002-04-23 |
| 6376308 | Process for fabricating an EEPROM device having a pocket substrate region | David K. Foote, Bharath Rangarajan, George J. Kluth | 2002-04-23 |