Issued Patents All Time
Showing 201–225 of 240 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6242305 | Process for fabricating a bit-line using buried diffusion isolation | David K. Foote, Hideki Komori, Bharath Rangarajan | 2001-06-05 |
| 6235628 | Method of forming dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide middle etch stop layer | Jerry Cheng | 2001-05-22 |
| 6211071 | Optimized trench/via profile for damascene filling | Todd P. Lukanc, Steven C. Avanzino | 2001-04-03 |
| 6207502 | Method of using source/drain nitride for periphery field oxide and bit-line oxide | Kenneth Wo-Wai Au, David K. Foote, Steven K. Park, Bharath Rangarajan | 2001-03-27 |
| 6207576 | Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide etch stop layer | Jerry Cheng | 2001-03-27 |
| 6207577 | Self-aligned dual damascene arrangement for metal interconnection with oxide dielectric layer and low k dielectric constant layer | Jerry Cheng, Darrell M. Erb | 2001-03-27 |
| 6200907 | Ultra-thin resist and barrier metal/oxide hard mask for metal etch | Christopher F. Lyons, Khanh B. Nguyen, Scott A. Bell, Harry J. Levinson, Chih-Yuh Yang | 2001-03-13 |
| 6184128 | Method using a thin resist mask for dual damascene stop layer etch | Christopher F. Lyons, Khanh B. Nguyen, Scott A. Bell, Harry J. Levinson, Chih-Yuh Yang | 2001-02-06 |
| 6171763 | Ultra-thin resist and oxide/nitride hard mask for metal etch | Christopher F. Lyons, Khanh B. Nguyen, Scott A. Bell, Harry J. Levinson, Chih-Yuh Yang | 2001-01-09 |
| 6168993 | Process for fabricating a semiconductor device having a graded junction | David K. Foote, Bharath Rangarajan, George J. Kluth | 2001-01-02 |
| 6165695 | Thin resist with amorphous silicon hard mask for via etch application | Chih-Yuh Yang, Christopher F. Lyons, Harry J. Levinson, Khanh B. Nguyen, Scott A. Bell | 2000-12-26 |
| 6162587 | Thin resist with transition metal hard mask for via etch application | Chih-Yuh Yang, Christopher F. Lyons, Harry J. Levinson, Khanh B. Nguyen, Scott A. Bell | 2000-12-19 |
| 6156658 | Ultra-thin resist and silicon/oxide hard mask for metal etch | Christopher F. Lyons, Khanh B. Nguyen, Scott A. Bell, Harry J. Levinson, Chih-Yuh Yang | 2000-12-05 |
| 6156643 | Method of forming a dual damascene trench and borderless via structure | Simon S. Chan, Todd P. Lukanc | 2000-12-05 |
| 6153514 | Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer | Jerry Cheng, Todd P. Lukanc | 2000-11-28 |
| 6140023 | Method for transferring patterns created by lithography | Harry J. Levinson, Scott A. Bell, Christopher F. Lyons, Khanh B. Nguyen, Chih-Yuh Yang | 2000-10-31 |
| 6140706 | Semiconductor device and method of manufacturing without damaging HSQ layer and metal pattern utilizing multiple dielectric layers | Simon S. Chan, Susan H. Chen | 2000-10-31 |
| 6127070 | Thin resist with nitride hard mask for via etch application | Chih-Yuh Yang, Christopher F. Lyons, Harry J. Levinson, Khanh B. Nguyen, Scott A. Bell | 2000-10-03 |
| 6124201 | Method for manufacturing semiconductors with self-aligning vias | Robin Cheung, Mark S. Chang, Richard J. Huang, Angela T. Hui | 2000-09-26 |
| 6121663 | Local interconnects for improved alignment tolerance and size reduction | William G. En, Darin A. Chan, David K. Foote, Minh Van Ngo | 2000-09-19 |
| 6121150 | Sputter-resistant hardmask for damascene trench/via formation | Steven C. Avanzino | 2000-09-19 |
| 6121149 | Optimized trench/via profile for damascene filling | Todd P. Lukanc, Steven C. Avanzino | 2000-09-19 |
| 6117781 | Optimized trench/via profile for damascene processing | Todd P. Lukanc, Steven C. Avanzino | 2000-09-12 |
| 6117782 | Optimized trench/via profile for damascene filling | Todd P. Lukanc, Steven C. Avanzino | 2000-09-12 |
| 6114235 | Multipurpose cap layer dielectric | David K. Foote, Minh Van Ngo, Christopher F. Lyons, Raymond T. Lee, William G. En +2 more | 2000-09-05 |