Issued Patents All Time
Showing 176–200 of 240 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6372635 | Method for making a slot via filled dual damascene low k interconnect structure without middle stop layer | Lynne A. Okada, Ramkumar Subramanian, Calvin T. Gabriel | 2002-04-16 |
| 6372631 | Method of making a via filled dual damascene structure without middle stop layer | Lynne A. Okada, Ramkumar Subramanian, Calvin T. Gabriel | 2002-04-16 |
| 6365505 | Method of making a slot via filled dual damascene structure with middle stop layer | Lynne A. Okada, Ramkumar Subramanian, Calvin T. Gabriel | 2002-04-02 |
| 6362052 | Use of an etch to reduce the thickness and around the edges of a resist mask during the creation of a memory cell | Bharath Rangarajan, George J. Kluth, Ursula Q. Quinto | 2002-03-26 |
| 6359307 | Method for forming self-aligned contacts and interconnection lines using dual damascene techniques | Hiroyuki Kinoshita, Kashmir Sahota, Yu Sun, Wenge Yang | 2002-03-19 |
| 6358362 | Methods and arrangements for determining an endpoint for an in-situ local interconnect etching process | William G. En, Allison Holbrook | 2002-03-19 |
| 6355575 | Semiconductor device and method of manufacturing without damaging HSQ layer and metal pattern | Simon S. Chan, Susan H. Chen | 2002-03-12 |
| 6348379 | Method of forming self-aligned contacts using consumable spacers | Ramkumar Subramanian, Yu Sun | 2002-02-19 |
| 6348406 | Method for using a low dielectric constant layer as a semiconductor anti-reflective coating | Ramkumar Subramanian, Minh Van Ngo, Kashmir Sahota, YongZhong Hu, Hiroyuki Kinoshita +1 more | 2002-02-19 |
| 6329701 | Semiconductor device comprising copper interconnects with reduced in-line diffusion | Minh Van Ngo | 2001-12-11 |
| 6326268 | Method of fabricating a MONOS flash cell using shallow trench isolation | Steven K. Park, Bharath Rangarajan | 2001-12-04 |
| 6319834 | Method and apparatus for improved planarity metallization by electroplating and CMP | Darrell M. Erb, Steven C. Avanzino | 2001-11-20 |
| 6312874 | Method for forming a dual damascene trench and underlying borderless via in low dielectric constant materials | Simon S. Chan, Todd P. Lukanc | 2001-11-06 |
| 6313018 | Process for fabricating semiconductor device including antireflective etch stop layer | David K. Foote, Myron R. Cagan, Subhash Gupta | 2001-11-06 |
| 6309955 | Method for using a CVD organic barc as a hard mask during via etch | Ramkumar Subramanian, Todd P. Lukanc, Lynne A. Okada | 2001-10-30 |
| 6309926 | Thin resist with nitride hard mask for gate etch application | Scott A. Bell, Christopher F. Lyons, Harry J. Levinson, Khanh B. Nguyen, Chih-Yuh Yang | 2001-10-30 |
| 6306560 | Ultra-thin resist and SiON/oxide hard mask for metal etch | Christopher F. Lyons, Khanh B. Nguyen, Scott A. Bell, Harry J. Levinson, Chih-Yuh Yang | 2001-10-23 |
| 6306713 | Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer | YongZhong Hu, Wenge Yang, Yu Sun, Hiroyuki Kinoshita | 2001-10-23 |
| 6303949 | Method and system for providing electrical insulation for local interconnect in a logic circuit | William G. En, Sunil Mehta, Stewart Logie | 2001-10-16 |
| 6297143 | Process for forming a bit-line in a MONOS device | David K. Foote, Bharath Rangarajan, Steven K. Park | 2001-10-02 |
| 6297167 | In-situ etch of multiple layers during formation of local interconnects | James Kai, William G. En | 2001-10-02 |
| 6291887 | Dual damascene arrangements for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer | Jerry Cheng, Todd P. Lukanc | 2001-09-18 |
| 6271087 | Method for forming self-aligned contacts and local interconnects using self-aligned local interconnects | Hiroyuki Kinoshita, YongZhong Hu, Yu Sun | 2001-08-07 |
| 6261952 | Method of forming copper interconnects with reduced in-line diffusion | Minh Van Ngo | 2001-07-17 |
| 6255735 | Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers | Jerry Cheng, Simon S. Chan, Todd P. Lukanc | 2001-07-03 |