Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6548336 | Planarization of a polysilicon layer surface by chemical mechanical polish to improve lithography and silicide formation | Steven C. Avanzino | 2003-04-15 |
| 6537881 | Process for fabricating a non-volatile memory device | Bharath Rangarajan, David K. Foote, Fei Wang | 2003-03-25 |
| 6346466 | Planarization of a polysilicon layer surface by chemical mechanical polish to improve lithography and silicide formation | Steven C. Avanzino | 2002-02-12 |
| 6326268 | Method of fabricating a MONOS flash cell using shallow trench isolation | Fei Wang, Bharath Rangarajan | 2001-12-04 |
| 6323516 | Flash memory device and fabrication method having a high coupling ratio | Larry Wang | 2001-11-27 |
| 6297143 | Process for forming a bit-line in a MONOS device | David K. Foote, Bharath Rangarajan, Fei Wang | 2001-10-02 |
| 6258669 | Methods and arrangements for improved formation of control and floating gates in non-volatile memory semiconductor devices | — | 2001-07-10 |
| 6248635 | Process for fabricating a bit-line in a monos device using a dual layer hard mask | David K. Foote, Hideki Komori, Bharath Rangarajan | 2001-06-19 |
| 6218227 | Method to generate a MONOS type flash cell using polycrystalline silicon as an ONO top layer | Arvind Halliyal, Hideki Komori | 2001-04-17 |
| 6207502 | Method of using source/drain nitride for periphery field oxide and bit-line oxide | Kenneth Wo-Wai Au, David K. Foote, Fei Wang, Bharath Rangarajan | 2001-03-27 |
| 6180538 | Process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device using rapid-thermal-chemical-vapor-deposition | Arvind Halliyal, Robert B. Ogle, Kenneth Wo-Wai Au | 2001-01-30 |