Issued Patents All Time
Showing 101–125 of 240 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7776682 | Ordered porosity to direct memory element formation | Alexander H. Nickel, Suzette K. Pangrle, Steven C. Avanzino, Jeffrey A. Shields, Minh Quoc Tran +2 more | 2010-08-17 |
| 7732276 | Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications | Shenqing Fang, Jihwan P. Choi, Calvin T. Gabriel, Angela T. Hui, Alexander H. Nickel +4 more | 2010-06-08 |
| 7622389 | Selective contact formation using masking and resist patterning techniques | Kyunghoon Min, Mark S. Chang, Ning Cheng, Brian Osborn, Kevin Song +3 more | 2009-11-24 |
| 7385460 | Combined electrostatic and optical waveguide based microfluidic chip systems and methods | David Erickson, Changhuei Yang | 2008-06-10 |
| 7279410 | Method for forming inlaid structures for IC interconnections | Lynne A. Okada, James Kai | 2007-10-09 |
| 7256499 | Ultra low dielectric constant integrated circuit system | Lu You, Minh Quoc Tran, Lynne A. Okada | 2007-08-14 |
| 7232765 | Utilization of a Ta-containing cap over copper to facilitate concurrent formation of copper vias and memory element structures | Steven C. Avanzino, Nicholas H. Tripsas, Jeffrey A. Shields, Richard Kingsborough, William Leonard +1 more | 2007-06-19 |
| 7208418 | Sealing sidewall pores in low-k dielectrics | Lynne A. Okada, Minh Quoc Tran, Lu You | 2007-04-24 |
| 7132363 | Stabilizing fluorine etching of low-k materials | Kai Yang, Darrell M. Erb | 2006-11-07 |
| 7038320 | Single damascene integration scheme for preventing copper contamination of dielectric layer | Lu You, Minh Van Ngo | 2006-05-02 |
| 7001840 | Interconnect with multiple layers of conductive material with grain boundary between the layers | Minh Quoc Tran, Lu You, Lynne A. Okada | 2006-02-21 |
| 6939793 | Dual damascene integration scheme for preventing copper contamination of dielectric layer | Lu You, Christy Mei-Chu Woo | 2005-09-06 |
| 6878622 | Method for forming SAC using a dielectric as a BARC and FICD enlarger | Wenge Yang, Ramkumar Subramanian, Lewis Shen | 2005-04-12 |
| 6833625 | Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect | Pin-Chin Connie Wang | 2004-12-21 |
| 6770559 | Method of forming wiring by implantation of seed layer material | Ercan Adem, Joffre F. Bernard | 2004-08-03 |
| 6768204 | Self-aligned conductive plugs in a semiconductor device | Todd P. Lukanc, Darrell M. Erb | 2004-07-27 |
| 6767827 | Method for forming dual inlaid structures for IC interconnections | Lynne A. Okada, James Kai | 2004-07-27 |
| 6756300 | Method for forming dual damascene interconnect structure | Jerry Cheng, Lynne A. Okada, Minh Quoc Tran, Lu You | 2004-06-29 |
| 6756303 | Diffusion barrier and method for its production | Darrell M. Erb | 2004-06-29 |
| 6740566 | Ultra-thin resist shallow trench process using high selectivity nitride etch | Christopher F. Lyons, Scott A. Bell, Harry J. Levinson, Khanh B. Nguyen, Chih-Yuh Yang | 2004-05-25 |
| 6699792 | Polymer spacers for creating small geometry space and method of manufacture thereof | Lu You, Lynne A. Okada | 2004-03-02 |
| 6689684 | Cu damascene interconnections using barrier/capping layer | Lu You, Richard J. Huang | 2004-02-10 |
| 6677679 | Use of SiO2/Sin for preventing copper contamination of low-k dielectric layers | Lu You, Dawn Hopper | 2004-01-13 |
| 6670265 | Low K dielectic etch in high density plasma etcher | James Kai, Angela T. Hui | 2003-12-30 |
| 6664185 | Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect | Pin-Chin Connie Wang | 2003-12-16 |